From 36e53ad8a14f2c726e5a3c85c6fd5e2d2dd358d4 Mon Sep 17 00:00:00 2001
From: danghvu <danghvu@gmail.com>
Date: Sun, 31 Jan 2016 16:22:20 -0600
Subject: [PATCH] Fix arm & arm64 memleaks

---
 qemu/hw/arm/tosa.c                |  2 +-
 qemu/hw/arm/virt.c                |  2 +-
 qemu/target-arm/unicorn_aarch64.c | 18 ++++++++++++++++++
 qemu/target-arm/unicorn_arm.c     | 18 ++++++++++++++++++
 qemu/unicorn_common.h             |  1 +
 5 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/qemu/hw/arm/tosa.c b/qemu/hw/arm/tosa.c
index fe9eaf6e..8630e46e 100644
--- a/qemu/hw/arm/tosa.c
+++ b/qemu/hw/arm/tosa.c
@@ -20,7 +20,7 @@
 static int tosa_init(struct uc_struct *uc, MachineState *machine)
 {
     //cpu_arm_init(uc, "pxa255");
-    cpu_arm_init(uc, "cortex-a15"); // FIXME
+    uc->cpu = cpu_arm_init(uc, "cortex-a15"); // FIXME
 
     return 0;
 }
diff --git a/qemu/hw/arm/virt.c b/qemu/hw/arm/virt.c
index 554e89d7..e2a68412 100644
--- a/qemu/hw/arm/virt.c
+++ b/qemu/hw/arm/virt.c
@@ -54,7 +54,7 @@ static int machvirt_init(struct uc_struct *uc, MachineState *machine)
             return -1;
         }
 
-        cpuobj = object_new(uc, object_class_get_name(oc));
+        uc->cpu = cpuobj = object_new(uc, object_class_get_name(oc));
         object_property_set_bool(uc, cpuobj, true, "realized", NULL);
     }
 
diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c
index 0123b5cb..00f71c6a 100644
--- a/qemu/target-arm/unicorn_aarch64.c
+++ b/qemu/target-arm/unicorn_aarch64.c
@@ -25,6 +25,23 @@ static void arm64_set_pc(struct uc_struct *uc, uint64_t address)
     ((CPUARMState *)uc->current_cpu->env_ptr)->pc = address;
 }
 
+void arm64_release(void* ctx);
+
+void arm64_release(void* ctx)
+{
+    TCGContext *s = (TCGContext *) ctx;
+
+    g_free(s->tb_ctx.tbs);
+    struct uc_struct* uc = s->uc;
+    ARMCPU* cpu = (ARMCPU*) uc->cpu;
+    g_free(cpu->cpreg_indexes);
+    g_free(cpu->cpreg_values);
+    g_free(cpu->cpreg_vmstate_indexes);
+    g_free(cpu->cpreg_vmstate_values);
+
+    release_common(ctx);
+}
+
 void arm64_reg_reset(struct uc_struct *uc)
 {
     CPUArchState *env = first_cpu->env_ptr;
@@ -103,5 +120,6 @@ void arm64_uc_init(struct uc_struct* uc)
     uc->reg_write = arm64_reg_write;
     uc->reg_reset = arm64_reg_reset;
     uc->set_pc = arm64_set_pc;
+    uc->release = arm64_release;
     uc_common_init(uc);
 }
diff --git a/qemu/target-arm/unicorn_arm.c b/qemu/target-arm/unicorn_arm.c
index 1c4004af..22c35cf9 100644
--- a/qemu/target-arm/unicorn_arm.c
+++ b/qemu/target-arm/unicorn_arm.c
@@ -25,6 +25,23 @@ static void arm_set_pc(struct uc_struct *uc, uint64_t address)
     ((CPUARMState *)uc->current_cpu->env_ptr)->regs[15] = address;
 }
 
+void arm_release(void* ctx);
+
+void arm_release(void* ctx)
+{
+    TCGContext *s = (TCGContext *) ctx;
+
+    g_free(s->tb_ctx.tbs);
+    struct uc_struct* uc = s->uc;
+    ARMCPU* cpu = (ARMCPU*) uc->cpu;
+    g_free(cpu->cpreg_indexes);
+    g_free(cpu->cpreg_values);
+    g_free(cpu->cpreg_vmstate_indexes);
+    g_free(cpu->cpreg_vmstate_values);
+
+    release_common(ctx);
+}
+
 void arm_reg_reset(struct uc_struct *uc)
 {
     (void)uc;
@@ -134,5 +151,6 @@ void arm_uc_init(struct uc_struct* uc)
     uc->reg_reset = arm_reg_reset;
     uc->set_pc = arm_set_pc;
     uc->stop_interrupt = arm_stop_interrupt;
+    uc->release = arm_release;
     uc_common_init(uc);
 }
diff --git a/qemu/unicorn_common.h b/qemu/unicorn_common.h
index adccbe01..a9fb5176 100644
--- a/qemu/unicorn_common.h
+++ b/qemu/unicorn_common.h
@@ -42,6 +42,7 @@ static void release_common(void *t)
     g_free(def->args_ct);
     g_free(def->sorted_args);
     g_free(s->tcg_op_defs);
+
     TCGPool *po, *to;
     for (po = s->pool_first; po; po = to) {
         to = po->next;