From c6158b8628ff443506fe3333fafa83df2cf41678 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matheus=20C=2E=20Fran=C3=A7a?= Date: Thu, 23 Mar 2023 10:09:41 -0300 Subject: [PATCH 1/3] zig consts --- bindings/Makefile | 1 + bindings/const_generator.py | 20 + bindings/zig/README.md | 10 + bindings/zig/unicorn/arm64_const.zig | 337 +++++ bindings/zig/unicorn/arm_const.zig | 196 +++ bindings/zig/unicorn/m68k_const.zig | 41 + bindings/zig/unicorn/mips_const.zig | 239 ++++ bindings/zig/unicorn/ppc_const.zig | 408 ++++++ bindings/zig/unicorn/riscv_const.zig | 289 +++++ bindings/zig/unicorn/s390x_const.zig | 126 ++ bindings/zig/unicorn/sparc_const.zig | 138 ++ bindings/zig/unicorn/tricore_const.zig | 128 ++ bindings/zig/unicorn/unicorn.zig | 13 + bindings/zig/unicorn/unicorn_const.zig | 144 +++ bindings/zig/unicorn/x86_const.zig | 1632 ++++++++++++++++++++++++ 15 files changed, 3722 insertions(+) create mode 100644 bindings/zig/README.md create mode 100644 bindings/zig/unicorn/arm64_const.zig create mode 100644 bindings/zig/unicorn/arm_const.zig create mode 100644 bindings/zig/unicorn/m68k_const.zig create mode 100644 bindings/zig/unicorn/mips_const.zig create mode 100644 bindings/zig/unicorn/ppc_const.zig create mode 100644 bindings/zig/unicorn/riscv_const.zig create mode 100644 bindings/zig/unicorn/s390x_const.zig create mode 100644 bindings/zig/unicorn/sparc_const.zig create mode 100644 bindings/zig/unicorn/tricore_const.zig create mode 100644 bindings/zig/unicorn/unicorn.zig create mode 100644 bindings/zig/unicorn/unicorn_const.zig create mode 100644 bindings/zig/unicorn/x86_const.zig diff --git a/bindings/Makefile b/bindings/Makefile index bc5fb243..8c2ee2c2 100644 --- a/bindings/Makefile +++ b/bindings/Makefile @@ -26,6 +26,7 @@ build: $(MAKE) -C ruby gen_const python3 const_generator.py dotnet python3 const_generator.py pascal + python3 const_generator.py zig install: build $(MAKE) -C python install diff --git a/bindings/const_generator.py b/bindings/const_generator.py index 2a74c864..4c5d1e76 100644 --- a/bindings/const_generator.py +++ b/bindings/const_generator.py @@ -129,6 +129,26 @@ template = { 'comment_open': '//', 'comment_close': '', }, + 'zig': { + 'header': "// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT\n\npub const %sConst = enum(c_int) {\n", + 'footer': "\n};\n", + 'line_format': '\t%s = %s,\n', + 'out_file': './zig/unicorn/%s_const.zig', + # prefixes for constant filenames of all archs - case sensitive + 'arm.h': 'arm', + 'arm64.h': 'arm64', + 'mips.h': 'mips', + 'x86.h': 'x86', + 'sparc.h': 'sparc', + 'm68k.h': 'm68k', + 'ppc.h': 'ppc', + 'riscv.h': 'riscv', + 's390x.h' : 's390x', + 'tricore.h' : 'tricore', + 'unicorn.h': 'unicorn', + 'comment_open': '//', + 'comment_close': '', + }, } # markup for comments to be added to autogen files diff --git a/bindings/zig/README.md b/bindings/zig/README.md new file mode 100644 index 00000000..47bdda0e --- /dev/null +++ b/bindings/zig/README.md @@ -0,0 +1,10 @@ +# Unicorn-engine-Zig + +[Zig](https://ziglang.org/) bindings for the [Unicorn](http://www.unicorn-engine.org/) emulator with utility functions. + +*Unicorn* is a lightweight multi-platform, multi-architecture CPU emulator framework +based on [QEMU](http://www.qemu.org/). + +## How to use + +Add to your project the file `unicorn/unicorn.zig` that will manage all the available architectures. \ No newline at end of file diff --git a/bindings/zig/unicorn/arm64_const.zig b/bindings/zig/unicorn/arm64_const.zig new file mode 100644 index 00000000..54aa4030 --- /dev/null +++ b/bindings/zig/unicorn/arm64_const.zig @@ -0,0 +1,337 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const arm64Const = enum(c_int) { + +// ARM64 CPU + + CPU_ARM64_A57 = 0, + CPU_ARM64_A53 = 1, + CPU_ARM64_A72 = 2, + CPU_ARM64_MAX = 3, + CPU_ARM64_ENDING = 4, + +// ARM64 registers + + ARM64_REG_INVALID = 0, + ARM64_REG_X29 = 1, + ARM64_REG_X30 = 2, + ARM64_REG_NZCV = 3, + ARM64_REG_SP = 4, + ARM64_REG_WSP = 5, + ARM64_REG_WZR = 6, + ARM64_REG_XZR = 7, + ARM64_REG_B0 = 8, + ARM64_REG_B1 = 9, + ARM64_REG_B2 = 10, + ARM64_REG_B3 = 11, + ARM64_REG_B4 = 12, + ARM64_REG_B5 = 13, + ARM64_REG_B6 = 14, + ARM64_REG_B7 = 15, + ARM64_REG_B8 = 16, + ARM64_REG_B9 = 17, + ARM64_REG_B10 = 18, + ARM64_REG_B11 = 19, + ARM64_REG_B12 = 20, + ARM64_REG_B13 = 21, + ARM64_REG_B14 = 22, + ARM64_REG_B15 = 23, + ARM64_REG_B16 = 24, + ARM64_REG_B17 = 25, + ARM64_REG_B18 = 26, + ARM64_REG_B19 = 27, + ARM64_REG_B20 = 28, + ARM64_REG_B21 = 29, + ARM64_REG_B22 = 30, + ARM64_REG_B23 = 31, + ARM64_REG_B24 = 32, + ARM64_REG_B25 = 33, + ARM64_REG_B26 = 34, + ARM64_REG_B27 = 35, + ARM64_REG_B28 = 36, + ARM64_REG_B29 = 37, + ARM64_REG_B30 = 38, + ARM64_REG_B31 = 39, + ARM64_REG_D0 = 40, + ARM64_REG_D1 = 41, + ARM64_REG_D2 = 42, + ARM64_REG_D3 = 43, + ARM64_REG_D4 = 44, + ARM64_REG_D5 = 45, + ARM64_REG_D6 = 46, + ARM64_REG_D7 = 47, + ARM64_REG_D8 = 48, + ARM64_REG_D9 = 49, + ARM64_REG_D10 = 50, + ARM64_REG_D11 = 51, + ARM64_REG_D12 = 52, + ARM64_REG_D13 = 53, + ARM64_REG_D14 = 54, + ARM64_REG_D15 = 55, + ARM64_REG_D16 = 56, + ARM64_REG_D17 = 57, + ARM64_REG_D18 = 58, + ARM64_REG_D19 = 59, + ARM64_REG_D20 = 60, + ARM64_REG_D21 = 61, + ARM64_REG_D22 = 62, + ARM64_REG_D23 = 63, + ARM64_REG_D24 = 64, + ARM64_REG_D25 = 65, + ARM64_REG_D26 = 66, + ARM64_REG_D27 = 67, + ARM64_REG_D28 = 68, + ARM64_REG_D29 = 69, + ARM64_REG_D30 = 70, + ARM64_REG_D31 = 71, + ARM64_REG_H0 = 72, + ARM64_REG_H1 = 73, + ARM64_REG_H2 = 74, + ARM64_REG_H3 = 75, + ARM64_REG_H4 = 76, + ARM64_REG_H5 = 77, + ARM64_REG_H6 = 78, + ARM64_REG_H7 = 79, + ARM64_REG_H8 = 80, + ARM64_REG_H9 = 81, + ARM64_REG_H10 = 82, + ARM64_REG_H11 = 83, + ARM64_REG_H12 = 84, + ARM64_REG_H13 = 85, + ARM64_REG_H14 = 86, + ARM64_REG_H15 = 87, + ARM64_REG_H16 = 88, + ARM64_REG_H17 = 89, + ARM64_REG_H18 = 90, + ARM64_REG_H19 = 91, + ARM64_REG_H20 = 92, + ARM64_REG_H21 = 93, + ARM64_REG_H22 = 94, + ARM64_REG_H23 = 95, + ARM64_REG_H24 = 96, + ARM64_REG_H25 = 97, + ARM64_REG_H26 = 98, + ARM64_REG_H27 = 99, + ARM64_REG_H28 = 100, + ARM64_REG_H29 = 101, + ARM64_REG_H30 = 102, + ARM64_REG_H31 = 103, + ARM64_REG_Q0 = 104, + ARM64_REG_Q1 = 105, + ARM64_REG_Q2 = 106, + ARM64_REG_Q3 = 107, + ARM64_REG_Q4 = 108, + ARM64_REG_Q5 = 109, + ARM64_REG_Q6 = 110, + ARM64_REG_Q7 = 111, + ARM64_REG_Q8 = 112, + ARM64_REG_Q9 = 113, + ARM64_REG_Q10 = 114, + ARM64_REG_Q11 = 115, + ARM64_REG_Q12 = 116, + ARM64_REG_Q13 = 117, + ARM64_REG_Q14 = 118, + ARM64_REG_Q15 = 119, + ARM64_REG_Q16 = 120, + ARM64_REG_Q17 = 121, + ARM64_REG_Q18 = 122, + ARM64_REG_Q19 = 123, + ARM64_REG_Q20 = 124, + ARM64_REG_Q21 = 125, + ARM64_REG_Q22 = 126, + ARM64_REG_Q23 = 127, + ARM64_REG_Q24 = 128, + ARM64_REG_Q25 = 129, + ARM64_REG_Q26 = 130, + ARM64_REG_Q27 = 131, + ARM64_REG_Q28 = 132, + ARM64_REG_Q29 = 133, + ARM64_REG_Q30 = 134, + ARM64_REG_Q31 = 135, + ARM64_REG_S0 = 136, + ARM64_REG_S1 = 137, + ARM64_REG_S2 = 138, + ARM64_REG_S3 = 139, + ARM64_REG_S4 = 140, + ARM64_REG_S5 = 141, + ARM64_REG_S6 = 142, + ARM64_REG_S7 = 143, + ARM64_REG_S8 = 144, + ARM64_REG_S9 = 145, + ARM64_REG_S10 = 146, + ARM64_REG_S11 = 147, + ARM64_REG_S12 = 148, + ARM64_REG_S13 = 149, + ARM64_REG_S14 = 150, + ARM64_REG_S15 = 151, + ARM64_REG_S16 = 152, + ARM64_REG_S17 = 153, + ARM64_REG_S18 = 154, + ARM64_REG_S19 = 155, + ARM64_REG_S20 = 156, + ARM64_REG_S21 = 157, + ARM64_REG_S22 = 158, + ARM64_REG_S23 = 159, + ARM64_REG_S24 = 160, + ARM64_REG_S25 = 161, + ARM64_REG_S26 = 162, + ARM64_REG_S27 = 163, + ARM64_REG_S28 = 164, + ARM64_REG_S29 = 165, + ARM64_REG_S30 = 166, + ARM64_REG_S31 = 167, + ARM64_REG_W0 = 168, + ARM64_REG_W1 = 169, + ARM64_REG_W2 = 170, + ARM64_REG_W3 = 171, + ARM64_REG_W4 = 172, + ARM64_REG_W5 = 173, + ARM64_REG_W6 = 174, + ARM64_REG_W7 = 175, + ARM64_REG_W8 = 176, + ARM64_REG_W9 = 177, + ARM64_REG_W10 = 178, + ARM64_REG_W11 = 179, + ARM64_REG_W12 = 180, + ARM64_REG_W13 = 181, + ARM64_REG_W14 = 182, + ARM64_REG_W15 = 183, + ARM64_REG_W16 = 184, + ARM64_REG_W17 = 185, + ARM64_REG_W18 = 186, + ARM64_REG_W19 = 187, + ARM64_REG_W20 = 188, + ARM64_REG_W21 = 189, + ARM64_REG_W22 = 190, + ARM64_REG_W23 = 191, + ARM64_REG_W24 = 192, + ARM64_REG_W25 = 193, + ARM64_REG_W26 = 194, + ARM64_REG_W27 = 195, + ARM64_REG_W28 = 196, + ARM64_REG_W29 = 197, + ARM64_REG_W30 = 198, + ARM64_REG_X0 = 199, + ARM64_REG_X1 = 200, + ARM64_REG_X2 = 201, + ARM64_REG_X3 = 202, + ARM64_REG_X4 = 203, + ARM64_REG_X5 = 204, + ARM64_REG_X6 = 205, + ARM64_REG_X7 = 206, + ARM64_REG_X8 = 207, + ARM64_REG_X9 = 208, + ARM64_REG_X10 = 209, + ARM64_REG_X11 = 210, + ARM64_REG_X12 = 211, + ARM64_REG_X13 = 212, + ARM64_REG_X14 = 213, + ARM64_REG_X15 = 214, + ARM64_REG_X16 = 215, + ARM64_REG_X17 = 216, + ARM64_REG_X18 = 217, + ARM64_REG_X19 = 218, + ARM64_REG_X20 = 219, + ARM64_REG_X21 = 220, + ARM64_REG_X22 = 221, + ARM64_REG_X23 = 222, + ARM64_REG_X24 = 223, + ARM64_REG_X25 = 224, + ARM64_REG_X26 = 225, + ARM64_REG_X27 = 226, + ARM64_REG_X28 = 227, + ARM64_REG_V0 = 228, + ARM64_REG_V1 = 229, + ARM64_REG_V2 = 230, + ARM64_REG_V3 = 231, + ARM64_REG_V4 = 232, + ARM64_REG_V5 = 233, + ARM64_REG_V6 = 234, + ARM64_REG_V7 = 235, + ARM64_REG_V8 = 236, + ARM64_REG_V9 = 237, + ARM64_REG_V10 = 238, + ARM64_REG_V11 = 239, + ARM64_REG_V12 = 240, + ARM64_REG_V13 = 241, + ARM64_REG_V14 = 242, + ARM64_REG_V15 = 243, + ARM64_REG_V16 = 244, + ARM64_REG_V17 = 245, + ARM64_REG_V18 = 246, + ARM64_REG_V19 = 247, + ARM64_REG_V20 = 248, + ARM64_REG_V21 = 249, + ARM64_REG_V22 = 250, + ARM64_REG_V23 = 251, + ARM64_REG_V24 = 252, + ARM64_REG_V25 = 253, + ARM64_REG_V26 = 254, + ARM64_REG_V27 = 255, + ARM64_REG_V28 = 256, + ARM64_REG_V29 = 257, + ARM64_REG_V30 = 258, + ARM64_REG_V31 = 259, + +// pseudo registers + ARM64_REG_PC = 260, + ARM64_REG_CPACR_EL1 = 261, + +// thread registers, depreciated, use UC_ARM64_REG_CP_REG instead + ARM64_REG_TPIDR_EL0 = 262, + ARM64_REG_TPIDRRO_EL0 = 263, + ARM64_REG_TPIDR_EL1 = 264, + ARM64_REG_PSTATE = 265, + +// exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead + ARM64_REG_ELR_EL0 = 266, + ARM64_REG_ELR_EL1 = 267, + ARM64_REG_ELR_EL2 = 268, + ARM64_REG_ELR_EL3 = 269, + +// stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead + ARM64_REG_SP_EL0 = 270, + ARM64_REG_SP_EL1 = 271, + ARM64_REG_SP_EL2 = 272, + ARM64_REG_SP_EL3 = 273, + +// other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead + ARM64_REG_TTBR0_EL1 = 274, + ARM64_REG_TTBR1_EL1 = 275, + ARM64_REG_ESR_EL0 = 276, + ARM64_REG_ESR_EL1 = 277, + ARM64_REG_ESR_EL2 = 278, + ARM64_REG_ESR_EL3 = 279, + ARM64_REG_FAR_EL0 = 280, + ARM64_REG_FAR_EL1 = 281, + ARM64_REG_FAR_EL2 = 282, + ARM64_REG_FAR_EL3 = 283, + ARM64_REG_PAR_EL1 = 284, + ARM64_REG_MAIR_EL1 = 285, + ARM64_REG_VBAR_EL0 = 286, + ARM64_REG_VBAR_EL1 = 287, + ARM64_REG_VBAR_EL2 = 288, + ARM64_REG_VBAR_EL3 = 289, + ARM64_REG_CP_REG = 290, + +// floating point control and status registers + ARM64_REG_FPCR = 291, + ARM64_REG_FPSR = 292, + ARM64_REG_ENDING = 293, + +// alias registers + ARM64_REG_IP0 = 215, + ARM64_REG_IP1 = 216, + ARM64_REG_FP = 1, + ARM64_REG_LR = 2, + +// ARM64 instructions + + ARM64_INS_INVALID = 0, + ARM64_INS_MRS = 1, + ARM64_INS_MSR = 2, + ARM64_INS_SYS = 3, + ARM64_INS_SYSL = 4, + ARM64_INS_ENDING = 5, + +}; diff --git a/bindings/zig/unicorn/arm_const.zig b/bindings/zig/unicorn/arm_const.zig new file mode 100644 index 00000000..2403e9a7 --- /dev/null +++ b/bindings/zig/unicorn/arm_const.zig @@ -0,0 +1,196 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const armConst = enum(c_int) { + +// ARM CPU + + CPU_ARM_926 = 0, + CPU_ARM_946 = 1, + CPU_ARM_1026 = 2, + CPU_ARM_1136_R2 = 3, + CPU_ARM_1136 = 4, + CPU_ARM_1176 = 5, + CPU_ARM_11MPCORE = 6, + CPU_ARM_CORTEX_M0 = 7, + CPU_ARM_CORTEX_M3 = 8, + CPU_ARM_CORTEX_M4 = 9, + CPU_ARM_CORTEX_M7 = 10, + CPU_ARM_CORTEX_M33 = 11, + CPU_ARM_CORTEX_R5 = 12, + CPU_ARM_CORTEX_R5F = 13, + CPU_ARM_CORTEX_A7 = 14, + CPU_ARM_CORTEX_A8 = 15, + CPU_ARM_CORTEX_A9 = 16, + CPU_ARM_CORTEX_A15 = 17, + CPU_ARM_TI925T = 18, + CPU_ARM_SA1100 = 19, + CPU_ARM_SA1110 = 20, + CPU_ARM_PXA250 = 21, + CPU_ARM_PXA255 = 22, + CPU_ARM_PXA260 = 23, + CPU_ARM_PXA261 = 24, + CPU_ARM_PXA262 = 25, + CPU_ARM_PXA270 = 26, + CPU_ARM_PXA270A0 = 27, + CPU_ARM_PXA270A1 = 28, + CPU_ARM_PXA270B0 = 29, + CPU_ARM_PXA270B1 = 30, + CPU_ARM_PXA270C0 = 31, + CPU_ARM_PXA270C5 = 32, + CPU_ARM_MAX = 33, + CPU_ARM_ENDING = 34, + +// ARM registers + + ARM_REG_INVALID = 0, + ARM_REG_APSR = 1, + ARM_REG_APSR_NZCV = 2, + ARM_REG_CPSR = 3, + ARM_REG_FPEXC = 4, + ARM_REG_FPINST = 5, + ARM_REG_FPSCR = 6, + ARM_REG_FPSCR_NZCV = 7, + ARM_REG_FPSID = 8, + ARM_REG_ITSTATE = 9, + ARM_REG_LR = 10, + ARM_REG_PC = 11, + ARM_REG_SP = 12, + ARM_REG_SPSR = 13, + ARM_REG_D0 = 14, + ARM_REG_D1 = 15, + ARM_REG_D2 = 16, + ARM_REG_D3 = 17, + ARM_REG_D4 = 18, + ARM_REG_D5 = 19, + ARM_REG_D6 = 20, + ARM_REG_D7 = 21, + ARM_REG_D8 = 22, + ARM_REG_D9 = 23, + ARM_REG_D10 = 24, + ARM_REG_D11 = 25, + ARM_REG_D12 = 26, + ARM_REG_D13 = 27, + ARM_REG_D14 = 28, + ARM_REG_D15 = 29, + ARM_REG_D16 = 30, + ARM_REG_D17 = 31, + ARM_REG_D18 = 32, + ARM_REG_D19 = 33, + ARM_REG_D20 = 34, + ARM_REG_D21 = 35, + ARM_REG_D22 = 36, + ARM_REG_D23 = 37, + ARM_REG_D24 = 38, + ARM_REG_D25 = 39, + ARM_REG_D26 = 40, + ARM_REG_D27 = 41, + ARM_REG_D28 = 42, + ARM_REG_D29 = 43, + ARM_REG_D30 = 44, + ARM_REG_D31 = 45, + ARM_REG_FPINST2 = 46, + ARM_REG_MVFR0 = 47, + ARM_REG_MVFR1 = 48, + ARM_REG_MVFR2 = 49, + ARM_REG_Q0 = 50, + ARM_REG_Q1 = 51, + ARM_REG_Q2 = 52, + ARM_REG_Q3 = 53, + ARM_REG_Q4 = 54, + ARM_REG_Q5 = 55, + ARM_REG_Q6 = 56, + ARM_REG_Q7 = 57, + ARM_REG_Q8 = 58, + ARM_REG_Q9 = 59, + ARM_REG_Q10 = 60, + ARM_REG_Q11 = 61, + ARM_REG_Q12 = 62, + ARM_REG_Q13 = 63, + ARM_REG_Q14 = 64, + ARM_REG_Q15 = 65, + ARM_REG_R0 = 66, + ARM_REG_R1 = 67, + ARM_REG_R2 = 68, + ARM_REG_R3 = 69, + ARM_REG_R4 = 70, + ARM_REG_R5 = 71, + ARM_REG_R6 = 72, + ARM_REG_R7 = 73, + ARM_REG_R8 = 74, + ARM_REG_R9 = 75, + ARM_REG_R10 = 76, + ARM_REG_R11 = 77, + ARM_REG_R12 = 78, + ARM_REG_S0 = 79, + ARM_REG_S1 = 80, + ARM_REG_S2 = 81, + ARM_REG_S3 = 82, + ARM_REG_S4 = 83, + ARM_REG_S5 = 84, + ARM_REG_S6 = 85, + ARM_REG_S7 = 86, + ARM_REG_S8 = 87, + ARM_REG_S9 = 88, + ARM_REG_S10 = 89, + ARM_REG_S11 = 90, + ARM_REG_S12 = 91, + ARM_REG_S13 = 92, + ARM_REG_S14 = 93, + ARM_REG_S15 = 94, + ARM_REG_S16 = 95, + ARM_REG_S17 = 96, + ARM_REG_S18 = 97, + ARM_REG_S19 = 98, + ARM_REG_S20 = 99, + ARM_REG_S21 = 100, + ARM_REG_S22 = 101, + ARM_REG_S23 = 102, + ARM_REG_S24 = 103, + ARM_REG_S25 = 104, + ARM_REG_S26 = 105, + ARM_REG_S27 = 106, + ARM_REG_S28 = 107, + ARM_REG_S29 = 108, + ARM_REG_S30 = 109, + ARM_REG_S31 = 110, + ARM_REG_C1_C0_2 = 111, + ARM_REG_C13_C0_2 = 112, + ARM_REG_C13_C0_3 = 113, + ARM_REG_IPSR = 114, + ARM_REG_MSP = 115, + ARM_REG_PSP = 116, + ARM_REG_CONTROL = 117, + ARM_REG_IAPSR = 118, + ARM_REG_EAPSR = 119, + ARM_REG_XPSR = 120, + ARM_REG_EPSR = 121, + ARM_REG_IEPSR = 122, + ARM_REG_PRIMASK = 123, + ARM_REG_BASEPRI = 124, + ARM_REG_BASEPRI_MAX = 125, + ARM_REG_FAULTMASK = 126, + ARM_REG_APSR_NZCVQ = 127, + ARM_REG_APSR_G = 128, + ARM_REG_APSR_NZCVQG = 129, + ARM_REG_IAPSR_NZCVQ = 130, + ARM_REG_IAPSR_G = 131, + ARM_REG_IAPSR_NZCVQG = 132, + ARM_REG_EAPSR_NZCVQ = 133, + ARM_REG_EAPSR_G = 134, + ARM_REG_EAPSR_NZCVQG = 135, + ARM_REG_XPSR_NZCVQ = 136, + ARM_REG_XPSR_G = 137, + ARM_REG_XPSR_NZCVQG = 138, + ARM_REG_CP_REG = 139, + ARM_REG_ENDING = 140, + +// alias registers + ARM_REG_R13 = 12, + ARM_REG_R14 = 10, + ARM_REG_R15 = 11, + ARM_REG_SB = 75, + ARM_REG_SL = 76, + ARM_REG_FP = 77, + ARM_REG_IP = 78, + +}; diff --git a/bindings/zig/unicorn/m68k_const.zig b/bindings/zig/unicorn/m68k_const.zig new file mode 100644 index 00000000..8514d848 --- /dev/null +++ b/bindings/zig/unicorn/m68k_const.zig @@ -0,0 +1,41 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const m68kConst = enum(c_int) { + +// M68K CPU + + CPU_M68K_M5206 = 0, + CPU_M68K_M68000 = 1, + CPU_M68K_M68020 = 2, + CPU_M68K_M68030 = 3, + CPU_M68K_M68040 = 4, + CPU_M68K_M68060 = 5, + CPU_M68K_M5208 = 6, + CPU_M68K_CFV4E = 7, + CPU_M68K_ANY = 8, + CPU_M68K_ENDING = 9, + +// M68K registers + + M68K_REG_INVALID = 0, + M68K_REG_A0 = 1, + M68K_REG_A1 = 2, + M68K_REG_A2 = 3, + M68K_REG_A3 = 4, + M68K_REG_A4 = 5, + M68K_REG_A5 = 6, + M68K_REG_A6 = 7, + M68K_REG_A7 = 8, + M68K_REG_D0 = 9, + M68K_REG_D1 = 10, + M68K_REG_D2 = 11, + M68K_REG_D3 = 12, + M68K_REG_D4 = 13, + M68K_REG_D5 = 14, + M68K_REG_D6 = 15, + M68K_REG_D7 = 16, + M68K_REG_SR = 17, + M68K_REG_PC = 18, + M68K_REG_ENDING = 19, + +}; diff --git a/bindings/zig/unicorn/mips_const.zig b/bindings/zig/unicorn/mips_const.zig new file mode 100644 index 00000000..39a8aaf9 --- /dev/null +++ b/bindings/zig/unicorn/mips_const.zig @@ -0,0 +1,239 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const mipsConst = enum(c_int) { + +// MIPS32 CPUS + + CPU_MIPS32_4KC = 0, + CPU_MIPS32_4KM = 1, + CPU_MIPS32_4KECR1 = 2, + CPU_MIPS32_4KEMR1 = 3, + CPU_MIPS32_4KEC = 4, + CPU_MIPS32_4KEM = 5, + CPU_MIPS32_24KC = 6, + CPU_MIPS32_24KEC = 7, + CPU_MIPS32_24KF = 8, + CPU_MIPS32_34KF = 9, + CPU_MIPS32_74KF = 10, + CPU_MIPS32_M14K = 11, + CPU_MIPS32_M14KC = 12, + CPU_MIPS32_P5600 = 13, + CPU_MIPS32_MIPS32R6_GENERIC = 14, + CPU_MIPS32_I7200 = 15, + CPU_MIPS32_ENDING = 16, + +// MIPS64 CPUS + + CPU_MIPS64_R4000 = 0, + CPU_MIPS64_VR5432 = 1, + CPU_MIPS64_5KC = 2, + CPU_MIPS64_5KF = 3, + CPU_MIPS64_20KC = 4, + CPU_MIPS64_MIPS64R2_GENERIC = 5, + CPU_MIPS64_5KEC = 6, + CPU_MIPS64_5KEF = 7, + CPU_MIPS64_I6400 = 8, + CPU_MIPS64_I6500 = 9, + CPU_MIPS64_LOONGSON_2E = 10, + CPU_MIPS64_LOONGSON_2F = 11, + CPU_MIPS64_MIPS64DSPR2 = 12, + CPU_MIPS64_ENDING = 13, + +// MIPS registers + + MIPS_REG_INVALID = 0, + +// General purpose registers + MIPS_REG_PC = 1, + MIPS_REG_0 = 2, + MIPS_REG_1 = 3, + MIPS_REG_2 = 4, + MIPS_REG_3 = 5, + MIPS_REG_4 = 6, + MIPS_REG_5 = 7, + MIPS_REG_6 = 8, + MIPS_REG_7 = 9, + MIPS_REG_8 = 10, + MIPS_REG_9 = 11, + MIPS_REG_10 = 12, + MIPS_REG_11 = 13, + MIPS_REG_12 = 14, + MIPS_REG_13 = 15, + MIPS_REG_14 = 16, + MIPS_REG_15 = 17, + MIPS_REG_16 = 18, + MIPS_REG_17 = 19, + MIPS_REG_18 = 20, + MIPS_REG_19 = 21, + MIPS_REG_20 = 22, + MIPS_REG_21 = 23, + MIPS_REG_22 = 24, + MIPS_REG_23 = 25, + MIPS_REG_24 = 26, + MIPS_REG_25 = 27, + MIPS_REG_26 = 28, + MIPS_REG_27 = 29, + MIPS_REG_28 = 30, + MIPS_REG_29 = 31, + MIPS_REG_30 = 32, + MIPS_REG_31 = 33, + +// DSP registers + MIPS_REG_DSPCCOND = 34, + MIPS_REG_DSPCARRY = 35, + MIPS_REG_DSPEFI = 36, + MIPS_REG_DSPOUTFLAG = 37, + MIPS_REG_DSPOUTFLAG16_19 = 38, + MIPS_REG_DSPOUTFLAG20 = 39, + MIPS_REG_DSPOUTFLAG21 = 40, + MIPS_REG_DSPOUTFLAG22 = 41, + MIPS_REG_DSPOUTFLAG23 = 42, + MIPS_REG_DSPPOS = 43, + MIPS_REG_DSPSCOUNT = 44, + +// ACC registers + MIPS_REG_AC0 = 45, + MIPS_REG_AC1 = 46, + MIPS_REG_AC2 = 47, + MIPS_REG_AC3 = 48, + +// COP registers + MIPS_REG_CC0 = 49, + MIPS_REG_CC1 = 50, + MIPS_REG_CC2 = 51, + MIPS_REG_CC3 = 52, + MIPS_REG_CC4 = 53, + MIPS_REG_CC5 = 54, + MIPS_REG_CC6 = 55, + MIPS_REG_CC7 = 56, + +// FPU registers + MIPS_REG_F0 = 57, + MIPS_REG_F1 = 58, + MIPS_REG_F2 = 59, + MIPS_REG_F3 = 60, + MIPS_REG_F4 = 61, + MIPS_REG_F5 = 62, + MIPS_REG_F6 = 63, + MIPS_REG_F7 = 64, + MIPS_REG_F8 = 65, + MIPS_REG_F9 = 66, + MIPS_REG_F10 = 67, + MIPS_REG_F11 = 68, + MIPS_REG_F12 = 69, + MIPS_REG_F13 = 70, + MIPS_REG_F14 = 71, + MIPS_REG_F15 = 72, + MIPS_REG_F16 = 73, + MIPS_REG_F17 = 74, + MIPS_REG_F18 = 75, + MIPS_REG_F19 = 76, + MIPS_REG_F20 = 77, + MIPS_REG_F21 = 78, + MIPS_REG_F22 = 79, + MIPS_REG_F23 = 80, + MIPS_REG_F24 = 81, + MIPS_REG_F25 = 82, + MIPS_REG_F26 = 83, + MIPS_REG_F27 = 84, + MIPS_REG_F28 = 85, + MIPS_REG_F29 = 86, + MIPS_REG_F30 = 87, + MIPS_REG_F31 = 88, + MIPS_REG_FCC0 = 89, + MIPS_REG_FCC1 = 90, + MIPS_REG_FCC2 = 91, + MIPS_REG_FCC3 = 92, + MIPS_REG_FCC4 = 93, + MIPS_REG_FCC5 = 94, + MIPS_REG_FCC6 = 95, + MIPS_REG_FCC7 = 96, + +// AFPR128 + MIPS_REG_W0 = 97, + MIPS_REG_W1 = 98, + MIPS_REG_W2 = 99, + MIPS_REG_W3 = 100, + MIPS_REG_W4 = 101, + MIPS_REG_W5 = 102, + MIPS_REG_W6 = 103, + MIPS_REG_W7 = 104, + MIPS_REG_W8 = 105, + MIPS_REG_W9 = 106, + MIPS_REG_W10 = 107, + MIPS_REG_W11 = 108, + MIPS_REG_W12 = 109, + MIPS_REG_W13 = 110, + MIPS_REG_W14 = 111, + MIPS_REG_W15 = 112, + MIPS_REG_W16 = 113, + MIPS_REG_W17 = 114, + MIPS_REG_W18 = 115, + MIPS_REG_W19 = 116, + MIPS_REG_W20 = 117, + MIPS_REG_W21 = 118, + MIPS_REG_W22 = 119, + MIPS_REG_W23 = 120, + MIPS_REG_W24 = 121, + MIPS_REG_W25 = 122, + MIPS_REG_W26 = 123, + MIPS_REG_W27 = 124, + MIPS_REG_W28 = 125, + MIPS_REG_W29 = 126, + MIPS_REG_W30 = 127, + MIPS_REG_W31 = 128, + MIPS_REG_HI = 129, + MIPS_REG_LO = 130, + MIPS_REG_P0 = 131, + MIPS_REG_P1 = 132, + MIPS_REG_P2 = 133, + MIPS_REG_MPL0 = 134, + MIPS_REG_MPL1 = 135, + MIPS_REG_MPL2 = 136, + MIPS_REG_CP0_CONFIG3 = 137, + MIPS_REG_CP0_USERLOCAL = 138, + MIPS_REG_CP0_STATUS = 139, + MIPS_REG_ENDING = 140, + MIPS_REG_ZERO = 2, + MIPS_REG_AT = 3, + MIPS_REG_V0 = 4, + MIPS_REG_V1 = 5, + MIPS_REG_A0 = 6, + MIPS_REG_A1 = 7, + MIPS_REG_A2 = 8, + MIPS_REG_A3 = 9, + MIPS_REG_T0 = 10, + MIPS_REG_T1 = 11, + MIPS_REG_T2 = 12, + MIPS_REG_T3 = 13, + MIPS_REG_T4 = 14, + MIPS_REG_T5 = 15, + MIPS_REG_T6 = 16, + MIPS_REG_T7 = 17, + MIPS_REG_S0 = 18, + MIPS_REG_S1 = 19, + MIPS_REG_S2 = 20, + MIPS_REG_S3 = 21, + MIPS_REG_S4 = 22, + MIPS_REG_S5 = 23, + MIPS_REG_S6 = 24, + MIPS_REG_S7 = 25, + MIPS_REG_T8 = 26, + MIPS_REG_T9 = 27, + MIPS_REG_K0 = 28, + MIPS_REG_K1 = 29, + MIPS_REG_GP = 30, + MIPS_REG_SP = 31, + MIPS_REG_FP = 32, + MIPS_REG_S8 = 32, + MIPS_REG_RA = 33, + MIPS_REG_HI0 = 45, + MIPS_REG_HI1 = 46, + MIPS_REG_HI2 = 47, + MIPS_REG_HI3 = 48, + MIPS_REG_LO0 = 45, + MIPS_REG_LO1 = 46, + MIPS_REG_LO2 = 47, + MIPS_REG_LO3 = 48, + +}; diff --git a/bindings/zig/unicorn/ppc_const.zig b/bindings/zig/unicorn/ppc_const.zig new file mode 100644 index 00000000..9a4dd61a --- /dev/null +++ b/bindings/zig/unicorn/ppc_const.zig @@ -0,0 +1,408 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const ppcConst = enum(c_int) { + +// PPC CPU + + CPU_PPC32_401 = 0, + CPU_PPC32_401A1 = 1, + CPU_PPC32_401B2 = 2, + CPU_PPC32_401C2 = 3, + CPU_PPC32_401D2 = 4, + CPU_PPC32_401E2 = 5, + CPU_PPC32_401F2 = 6, + CPU_PPC32_401G2 = 7, + CPU_PPC32_IOP480 = 8, + CPU_PPC32_COBRA = 9, + CPU_PPC32_403GA = 10, + CPU_PPC32_403GB = 11, + CPU_PPC32_403GC = 12, + CPU_PPC32_403GCX = 13, + CPU_PPC32_405D2 = 14, + CPU_PPC32_405D4 = 15, + CPU_PPC32_405CRA = 16, + CPU_PPC32_405CRB = 17, + CPU_PPC32_405CRC = 18, + CPU_PPC32_405EP = 19, + CPU_PPC32_405EZ = 20, + CPU_PPC32_405GPA = 21, + CPU_PPC32_405GPB = 22, + CPU_PPC32_405GPC = 23, + CPU_PPC32_405GPD = 24, + CPU_PPC32_405GPR = 25, + CPU_PPC32_405LP = 26, + CPU_PPC32_NPE405H = 27, + CPU_PPC32_NPE405H2 = 28, + CPU_PPC32_NPE405L = 29, + CPU_PPC32_NPE4GS3 = 30, + CPU_PPC32_STB03 = 31, + CPU_PPC32_STB04 = 32, + CPU_PPC32_STB25 = 33, + CPU_PPC32_X2VP4 = 34, + CPU_PPC32_X2VP20 = 35, + CPU_PPC32_440_XILINX = 36, + CPU_PPC32_440_XILINX_W_DFPU = 37, + CPU_PPC32_440EPA = 38, + CPU_PPC32_440EPB = 39, + CPU_PPC32_440EPX = 40, + CPU_PPC32_460EXB = 41, + CPU_PPC32_G2 = 42, + CPU_PPC32_G2H4 = 43, + CPU_PPC32_G2GP = 44, + CPU_PPC32_G2LS = 45, + CPU_PPC32_G2HIP3 = 46, + CPU_PPC32_G2HIP4 = 47, + CPU_PPC32_MPC603 = 48, + CPU_PPC32_G2LE = 49, + CPU_PPC32_G2LEGP = 50, + CPU_PPC32_G2LELS = 51, + CPU_PPC32_G2LEGP1 = 52, + CPU_PPC32_G2LEGP3 = 53, + CPU_PPC32_MPC5200_V10 = 54, + CPU_PPC32_MPC5200_V11 = 55, + CPU_PPC32_MPC5200_V12 = 56, + CPU_PPC32_MPC5200B_V20 = 57, + CPU_PPC32_MPC5200B_V21 = 58, + CPU_PPC32_E200Z5 = 59, + CPU_PPC32_E200Z6 = 60, + CPU_PPC32_E300C1 = 61, + CPU_PPC32_E300C2 = 62, + CPU_PPC32_E300C3 = 63, + CPU_PPC32_E300C4 = 64, + CPU_PPC32_MPC8343 = 65, + CPU_PPC32_MPC8343A = 66, + CPU_PPC32_MPC8343E = 67, + CPU_PPC32_MPC8343EA = 68, + CPU_PPC32_MPC8347T = 69, + CPU_PPC32_MPC8347P = 70, + CPU_PPC32_MPC8347AT = 71, + CPU_PPC32_MPC8347AP = 72, + CPU_PPC32_MPC8347ET = 73, + CPU_PPC32_MPC8347EP = 74, + CPU_PPC32_MPC8347EAT = 75, + CPU_PPC32_MPC8347EAP = 76, + CPU_PPC32_MPC8349 = 77, + CPU_PPC32_MPC8349A = 78, + CPU_PPC32_MPC8349E = 79, + CPU_PPC32_MPC8349EA = 80, + CPU_PPC32_MPC8377 = 81, + CPU_PPC32_MPC8377E = 82, + CPU_PPC32_MPC8378 = 83, + CPU_PPC32_MPC8378E = 84, + CPU_PPC32_MPC8379 = 85, + CPU_PPC32_MPC8379E = 86, + CPU_PPC32_E500_V10 = 87, + CPU_PPC32_E500_V20 = 88, + CPU_PPC32_E500V2_V10 = 89, + CPU_PPC32_E500V2_V20 = 90, + CPU_PPC32_E500V2_V21 = 91, + CPU_PPC32_E500V2_V22 = 92, + CPU_PPC32_E500V2_V30 = 93, + CPU_PPC32_E500MC = 94, + CPU_PPC32_MPC8533_V10 = 95, + CPU_PPC32_MPC8533_V11 = 96, + CPU_PPC32_MPC8533E_V10 = 97, + CPU_PPC32_MPC8533E_V11 = 98, + CPU_PPC32_MPC8540_V10 = 99, + CPU_PPC32_MPC8540_V20 = 100, + CPU_PPC32_MPC8540_V21 = 101, + CPU_PPC32_MPC8541_V10 = 102, + CPU_PPC32_MPC8541_V11 = 103, + CPU_PPC32_MPC8541E_V10 = 104, + CPU_PPC32_MPC8541E_V11 = 105, + CPU_PPC32_MPC8543_V10 = 106, + CPU_PPC32_MPC8543_V11 = 107, + CPU_PPC32_MPC8543_V20 = 108, + CPU_PPC32_MPC8543_V21 = 109, + CPU_PPC32_MPC8543E_V10 = 110, + CPU_PPC32_MPC8543E_V11 = 111, + CPU_PPC32_MPC8543E_V20 = 112, + CPU_PPC32_MPC8543E_V21 = 113, + CPU_PPC32_MPC8544_V10 = 114, + CPU_PPC32_MPC8544_V11 = 115, + CPU_PPC32_MPC8544E_V10 = 116, + CPU_PPC32_MPC8544E_V11 = 117, + CPU_PPC32_MPC8545_V20 = 118, + CPU_PPC32_MPC8545_V21 = 119, + CPU_PPC32_MPC8545E_V20 = 120, + CPU_PPC32_MPC8545E_V21 = 121, + CPU_PPC32_MPC8547E_V20 = 122, + CPU_PPC32_MPC8547E_V21 = 123, + CPU_PPC32_MPC8548_V10 = 124, + CPU_PPC32_MPC8548_V11 = 125, + CPU_PPC32_MPC8548_V20 = 126, + CPU_PPC32_MPC8548_V21 = 127, + CPU_PPC32_MPC8548E_V10 = 128, + CPU_PPC32_MPC8548E_V11 = 129, + CPU_PPC32_MPC8548E_V20 = 130, + CPU_PPC32_MPC8548E_V21 = 131, + CPU_PPC32_MPC8555_V10 = 132, + CPU_PPC32_MPC8555_V11 = 133, + CPU_PPC32_MPC8555E_V10 = 134, + CPU_PPC32_MPC8555E_V11 = 135, + CPU_PPC32_MPC8560_V10 = 136, + CPU_PPC32_MPC8560_V20 = 137, + CPU_PPC32_MPC8560_V21 = 138, + CPU_PPC32_MPC8567 = 139, + CPU_PPC32_MPC8567E = 140, + CPU_PPC32_MPC8568 = 141, + CPU_PPC32_MPC8568E = 142, + CPU_PPC32_MPC8572 = 143, + CPU_PPC32_MPC8572E = 144, + CPU_PPC32_E600 = 145, + CPU_PPC32_MPC8610 = 146, + CPU_PPC32_MPC8641 = 147, + CPU_PPC32_MPC8641D = 148, + CPU_PPC32_601_V0 = 149, + CPU_PPC32_601_V1 = 150, + CPU_PPC32_601_V2 = 151, + CPU_PPC32_602 = 152, + CPU_PPC32_603 = 153, + CPU_PPC32_603E_V1_1 = 154, + CPU_PPC32_603E_V1_2 = 155, + CPU_PPC32_603E_V1_3 = 156, + CPU_PPC32_603E_V1_4 = 157, + CPU_PPC32_603E_V2_2 = 158, + CPU_PPC32_603E_V3 = 159, + CPU_PPC32_603E_V4 = 160, + CPU_PPC32_603E_V4_1 = 161, + CPU_PPC32_603E7 = 162, + CPU_PPC32_603E7T = 163, + CPU_PPC32_603E7V = 164, + CPU_PPC32_603E7V1 = 165, + CPU_PPC32_603E7V2 = 166, + CPU_PPC32_603P = 167, + CPU_PPC32_604 = 168, + CPU_PPC32_604E_V1_0 = 169, + CPU_PPC32_604E_V2_2 = 170, + CPU_PPC32_604E_V2_4 = 171, + CPU_PPC32_604R = 172, + CPU_PPC32_740_V1_0 = 173, + CPU_PPC32_750_V1_0 = 174, + CPU_PPC32_740_V2_0 = 175, + CPU_PPC32_750_V2_0 = 176, + CPU_PPC32_740_V2_1 = 177, + CPU_PPC32_750_V2_1 = 178, + CPU_PPC32_740_V2_2 = 179, + CPU_PPC32_750_V2_2 = 180, + CPU_PPC32_740_V3_0 = 181, + CPU_PPC32_750_V3_0 = 182, + CPU_PPC32_740_V3_1 = 183, + CPU_PPC32_750_V3_1 = 184, + CPU_PPC32_740E = 185, + CPU_PPC32_750E = 186, + CPU_PPC32_740P = 187, + CPU_PPC32_750P = 188, + CPU_PPC32_750CL_V1_0 = 189, + CPU_PPC32_750CL_V2_0 = 190, + CPU_PPC32_750CX_V1_0 = 191, + CPU_PPC32_750CX_V2_0 = 192, + CPU_PPC32_750CX_V2_1 = 193, + CPU_PPC32_750CX_V2_2 = 194, + CPU_PPC32_750CXE_V2_1 = 195, + CPU_PPC32_750CXE_V2_2 = 196, + CPU_PPC32_750CXE_V2_3 = 197, + CPU_PPC32_750CXE_V2_4 = 198, + CPU_PPC32_750CXE_V2_4B = 199, + CPU_PPC32_750CXE_V3_0 = 200, + CPU_PPC32_750CXE_V3_1 = 201, + CPU_PPC32_750CXE_V3_1B = 202, + CPU_PPC32_750CXR = 203, + CPU_PPC32_750FL = 204, + CPU_PPC32_750FX_V1_0 = 205, + CPU_PPC32_750FX_V2_0 = 206, + CPU_PPC32_750FX_V2_1 = 207, + CPU_PPC32_750FX_V2_2 = 208, + CPU_PPC32_750FX_V2_3 = 209, + CPU_PPC32_750GL = 210, + CPU_PPC32_750GX_V1_0 = 211, + CPU_PPC32_750GX_V1_1 = 212, + CPU_PPC32_750GX_V1_2 = 213, + CPU_PPC32_750L_V2_0 = 214, + CPU_PPC32_750L_V2_1 = 215, + CPU_PPC32_750L_V2_2 = 216, + CPU_PPC32_750L_V3_0 = 217, + CPU_PPC32_750L_V3_2 = 218, + CPU_PPC32_745_V1_0 = 219, + CPU_PPC32_755_V1_0 = 220, + CPU_PPC32_745_V1_1 = 221, + CPU_PPC32_755_V1_1 = 222, + CPU_PPC32_745_V2_0 = 223, + CPU_PPC32_755_V2_0 = 224, + CPU_PPC32_745_V2_1 = 225, + CPU_PPC32_755_V2_1 = 226, + CPU_PPC32_745_V2_2 = 227, + CPU_PPC32_755_V2_2 = 228, + CPU_PPC32_745_V2_3 = 229, + CPU_PPC32_755_V2_3 = 230, + CPU_PPC32_745_V2_4 = 231, + CPU_PPC32_755_V2_4 = 232, + CPU_PPC32_745_V2_5 = 233, + CPU_PPC32_755_V2_5 = 234, + CPU_PPC32_745_V2_6 = 235, + CPU_PPC32_755_V2_6 = 236, + CPU_PPC32_745_V2_7 = 237, + CPU_PPC32_755_V2_7 = 238, + CPU_PPC32_745_V2_8 = 239, + CPU_PPC32_755_V2_8 = 240, + CPU_PPC32_7400_V1_0 = 241, + CPU_PPC32_7400_V1_1 = 242, + CPU_PPC32_7400_V2_0 = 243, + CPU_PPC32_7400_V2_1 = 244, + CPU_PPC32_7400_V2_2 = 245, + CPU_PPC32_7400_V2_6 = 246, + CPU_PPC32_7400_V2_7 = 247, + CPU_PPC32_7400_V2_8 = 248, + CPU_PPC32_7400_V2_9 = 249, + CPU_PPC32_7410_V1_0 = 250, + CPU_PPC32_7410_V1_1 = 251, + CPU_PPC32_7410_V1_2 = 252, + CPU_PPC32_7410_V1_3 = 253, + CPU_PPC32_7410_V1_4 = 254, + CPU_PPC32_7448_V1_0 = 255, + CPU_PPC32_7448_V1_1 = 256, + CPU_PPC32_7448_V2_0 = 257, + CPU_PPC32_7448_V2_1 = 258, + CPU_PPC32_7450_V1_0 = 259, + CPU_PPC32_7450_V1_1 = 260, + CPU_PPC32_7450_V1_2 = 261, + CPU_PPC32_7450_V2_0 = 262, + CPU_PPC32_7450_V2_1 = 263, + CPU_PPC32_7441_V2_1 = 264, + CPU_PPC32_7441_V2_3 = 265, + CPU_PPC32_7451_V2_3 = 266, + CPU_PPC32_7441_V2_10 = 267, + CPU_PPC32_7451_V2_10 = 268, + CPU_PPC32_7445_V1_0 = 269, + CPU_PPC32_7455_V1_0 = 270, + CPU_PPC32_7445_V2_1 = 271, + CPU_PPC32_7455_V2_1 = 272, + CPU_PPC32_7445_V3_2 = 273, + CPU_PPC32_7455_V3_2 = 274, + CPU_PPC32_7445_V3_3 = 275, + CPU_PPC32_7455_V3_3 = 276, + CPU_PPC32_7445_V3_4 = 277, + CPU_PPC32_7455_V3_4 = 278, + CPU_PPC32_7447_V1_0 = 279, + CPU_PPC32_7457_V1_0 = 280, + CPU_PPC32_7447_V1_1 = 281, + CPU_PPC32_7457_V1_1 = 282, + CPU_PPC32_7457_V1_2 = 283, + CPU_PPC32_7447A_V1_0 = 284, + CPU_PPC32_7457A_V1_0 = 285, + CPU_PPC32_7447A_V1_1 = 286, + CPU_PPC32_7457A_V1_1 = 287, + CPU_PPC32_7447A_V1_2 = 288, + CPU_PPC32_7457A_V1_2 = 289, + CPU_PPC32_ENDING = 290, + +// PPC64 CPU + + CPU_PPC64_E5500 = 0, + CPU_PPC64_E6500 = 1, + CPU_PPC64_970_V2_2 = 2, + CPU_PPC64_970FX_V1_0 = 3, + CPU_PPC64_970FX_V2_0 = 4, + CPU_PPC64_970FX_V2_1 = 5, + CPU_PPC64_970FX_V3_0 = 6, + CPU_PPC64_970FX_V3_1 = 7, + CPU_PPC64_970MP_V1_0 = 8, + CPU_PPC64_970MP_V1_1 = 9, + CPU_PPC64_POWER5_V2_1 = 10, + CPU_PPC64_POWER7_V2_3 = 11, + CPU_PPC64_POWER7_V2_1 = 12, + CPU_PPC64_POWER8E_V2_1 = 13, + CPU_PPC64_POWER8_V2_0 = 14, + CPU_PPC64_POWER8NVL_V1_0 = 15, + CPU_PPC64_POWER9_V1_0 = 16, + CPU_PPC64_POWER9_V2_0 = 17, + CPU_PPC64_POWER10_V1_0 = 18, + CPU_PPC64_ENDING = 19, + +// PPC registers + + PPC_REG_INVALID = 0, + +// General purpose registers + PPC_REG_PC = 1, + PPC_REG_0 = 2, + PPC_REG_1 = 3, + PPC_REG_2 = 4, + PPC_REG_3 = 5, + PPC_REG_4 = 6, + PPC_REG_5 = 7, + PPC_REG_6 = 8, + PPC_REG_7 = 9, + PPC_REG_8 = 10, + PPC_REG_9 = 11, + PPC_REG_10 = 12, + PPC_REG_11 = 13, + PPC_REG_12 = 14, + PPC_REG_13 = 15, + PPC_REG_14 = 16, + PPC_REG_15 = 17, + PPC_REG_16 = 18, + PPC_REG_17 = 19, + PPC_REG_18 = 20, + PPC_REG_19 = 21, + PPC_REG_20 = 22, + PPC_REG_21 = 23, + PPC_REG_22 = 24, + PPC_REG_23 = 25, + PPC_REG_24 = 26, + PPC_REG_25 = 27, + PPC_REG_26 = 28, + PPC_REG_27 = 29, + PPC_REG_28 = 30, + PPC_REG_29 = 31, + PPC_REG_30 = 32, + PPC_REG_31 = 33, + PPC_REG_CR0 = 34, + PPC_REG_CR1 = 35, + PPC_REG_CR2 = 36, + PPC_REG_CR3 = 37, + PPC_REG_CR4 = 38, + PPC_REG_CR5 = 39, + PPC_REG_CR6 = 40, + PPC_REG_CR7 = 41, + PPC_REG_FPR0 = 42, + PPC_REG_FPR1 = 43, + PPC_REG_FPR2 = 44, + PPC_REG_FPR3 = 45, + PPC_REG_FPR4 = 46, + PPC_REG_FPR5 = 47, + PPC_REG_FPR6 = 48, + PPC_REG_FPR7 = 49, + PPC_REG_FPR8 = 50, + PPC_REG_FPR9 = 51, + PPC_REG_FPR10 = 52, + PPC_REG_FPR11 = 53, + PPC_REG_FPR12 = 54, + PPC_REG_FPR13 = 55, + PPC_REG_FPR14 = 56, + PPC_REG_FPR15 = 57, + PPC_REG_FPR16 = 58, + PPC_REG_FPR17 = 59, + PPC_REG_FPR18 = 60, + PPC_REG_FPR19 = 61, + PPC_REG_FPR20 = 62, + PPC_REG_FPR21 = 63, + PPC_REG_FPR22 = 64, + PPC_REG_FPR23 = 65, + PPC_REG_FPR24 = 66, + PPC_REG_FPR25 = 67, + PPC_REG_FPR26 = 68, + PPC_REG_FPR27 = 69, + PPC_REG_FPR28 = 70, + PPC_REG_FPR29 = 71, + PPC_REG_FPR30 = 72, + PPC_REG_FPR31 = 73, + PPC_REG_LR = 74, + PPC_REG_XER = 75, + PPC_REG_CTR = 76, + PPC_REG_MSR = 77, + PPC_REG_FPSCR = 78, + PPC_REG_CR = 79, + PPC_REG_ENDING = 80, + +}; diff --git a/bindings/zig/unicorn/riscv_const.zig b/bindings/zig/unicorn/riscv_const.zig new file mode 100644 index 00000000..3e713449 --- /dev/null +++ b/bindings/zig/unicorn/riscv_const.zig @@ -0,0 +1,289 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const riscvConst = enum(c_int) { + +// RISCV32 CPU + + CPU_RISCV32_ANY = 0, + CPU_RISCV32_BASE32 = 1, + CPU_RISCV32_SIFIVE_E31 = 2, + CPU_RISCV32_SIFIVE_U34 = 3, + CPU_RISCV32_ENDING = 4, + +// RISCV64 CPU + + CPU_RISCV64_ANY = 0, + CPU_RISCV64_BASE64 = 1, + CPU_RISCV64_SIFIVE_E51 = 2, + CPU_RISCV64_SIFIVE_U54 = 3, + CPU_RISCV64_ENDING = 4, + +// RISCV registers + + RISCV_REG_INVALID = 0, + +// General purpose registers + RISCV_REG_X0 = 1, + RISCV_REG_X1 = 2, + RISCV_REG_X2 = 3, + RISCV_REG_X3 = 4, + RISCV_REG_X4 = 5, + RISCV_REG_X5 = 6, + RISCV_REG_X6 = 7, + RISCV_REG_X7 = 8, + RISCV_REG_X8 = 9, + RISCV_REG_X9 = 10, + RISCV_REG_X10 = 11, + RISCV_REG_X11 = 12, + RISCV_REG_X12 = 13, + RISCV_REG_X13 = 14, + RISCV_REG_X14 = 15, + RISCV_REG_X15 = 16, + RISCV_REG_X16 = 17, + RISCV_REG_X17 = 18, + RISCV_REG_X18 = 19, + RISCV_REG_X19 = 20, + RISCV_REG_X20 = 21, + RISCV_REG_X21 = 22, + RISCV_REG_X22 = 23, + RISCV_REG_X23 = 24, + RISCV_REG_X24 = 25, + RISCV_REG_X25 = 26, + RISCV_REG_X26 = 27, + RISCV_REG_X27 = 28, + RISCV_REG_X28 = 29, + RISCV_REG_X29 = 30, + RISCV_REG_X30 = 31, + RISCV_REG_X31 = 32, + +// RISCV CSR + RISCV_REG_USTATUS = 33, + RISCV_REG_UIE = 34, + RISCV_REG_UTVEC = 35, + RISCV_REG_USCRATCH = 36, + RISCV_REG_UEPC = 37, + RISCV_REG_UCAUSE = 38, + RISCV_REG_UTVAL = 39, + RISCV_REG_UIP = 40, + RISCV_REG_FFLAGS = 41, + RISCV_REG_FRM = 42, + RISCV_REG_FCSR = 43, + RISCV_REG_CYCLE = 44, + RISCV_REG_TIME = 45, + RISCV_REG_INSTRET = 46, + RISCV_REG_HPMCOUNTER3 = 47, + RISCV_REG_HPMCOUNTER4 = 48, + RISCV_REG_HPMCOUNTER5 = 49, + RISCV_REG_HPMCOUNTER6 = 50, + RISCV_REG_HPMCOUNTER7 = 51, + RISCV_REG_HPMCOUNTER8 = 52, + RISCV_REG_HPMCOUNTER9 = 53, + RISCV_REG_HPMCOUNTER10 = 54, + RISCV_REG_HPMCOUNTER11 = 55, + RISCV_REG_HPMCOUNTER12 = 56, + RISCV_REG_HPMCOUNTER13 = 57, + RISCV_REG_HPMCOUNTER14 = 58, + RISCV_REG_HPMCOUNTER15 = 59, + RISCV_REG_HPMCOUNTER16 = 60, + RISCV_REG_HPMCOUNTER17 = 61, + RISCV_REG_HPMCOUNTER18 = 62, + RISCV_REG_HPMCOUNTER19 = 63, + RISCV_REG_HPMCOUNTER20 = 64, + RISCV_REG_HPMCOUNTER21 = 65, + RISCV_REG_HPMCOUNTER22 = 66, + RISCV_REG_HPMCOUNTER23 = 67, + RISCV_REG_HPMCOUNTER24 = 68, + RISCV_REG_HPMCOUNTER25 = 69, + RISCV_REG_HPMCOUNTER26 = 70, + RISCV_REG_HPMCOUNTER27 = 71, + RISCV_REG_HPMCOUNTER28 = 72, + RISCV_REG_HPMCOUNTER29 = 73, + RISCV_REG_HPMCOUNTER30 = 74, + RISCV_REG_HPMCOUNTER31 = 75, + RISCV_REG_CYCLEH = 76, + RISCV_REG_TIMEH = 77, + RISCV_REG_INSTRETH = 78, + RISCV_REG_HPMCOUNTER3H = 79, + RISCV_REG_HPMCOUNTER4H = 80, + RISCV_REG_HPMCOUNTER5H = 81, + RISCV_REG_HPMCOUNTER6H = 82, + RISCV_REG_HPMCOUNTER7H = 83, + RISCV_REG_HPMCOUNTER8H = 84, + RISCV_REG_HPMCOUNTER9H = 85, + RISCV_REG_HPMCOUNTER10H = 86, + RISCV_REG_HPMCOUNTER11H = 87, + RISCV_REG_HPMCOUNTER12H = 88, + RISCV_REG_HPMCOUNTER13H = 89, + RISCV_REG_HPMCOUNTER14H = 90, + RISCV_REG_HPMCOUNTER15H = 91, + RISCV_REG_HPMCOUNTER16H = 92, + RISCV_REG_HPMCOUNTER17H = 93, + RISCV_REG_HPMCOUNTER18H = 94, + RISCV_REG_HPMCOUNTER19H = 95, + RISCV_REG_HPMCOUNTER20H = 96, + RISCV_REG_HPMCOUNTER21H = 97, + RISCV_REG_HPMCOUNTER22H = 98, + RISCV_REG_HPMCOUNTER23H = 99, + RISCV_REG_HPMCOUNTER24H = 100, + RISCV_REG_HPMCOUNTER25H = 101, + RISCV_REG_HPMCOUNTER26H = 102, + RISCV_REG_HPMCOUNTER27H = 103, + RISCV_REG_HPMCOUNTER28H = 104, + RISCV_REG_HPMCOUNTER29H = 105, + RISCV_REG_HPMCOUNTER30H = 106, + RISCV_REG_HPMCOUNTER31H = 107, + RISCV_REG_MCYCLE = 108, + RISCV_REG_MINSTRET = 109, + RISCV_REG_MCYCLEH = 110, + RISCV_REG_MINSTRETH = 111, + RISCV_REG_MVENDORID = 112, + RISCV_REG_MARCHID = 113, + RISCV_REG_MIMPID = 114, + RISCV_REG_MHARTID = 115, + RISCV_REG_MSTATUS = 116, + RISCV_REG_MISA = 117, + RISCV_REG_MEDELEG = 118, + RISCV_REG_MIDELEG = 119, + RISCV_REG_MIE = 120, + RISCV_REG_MTVEC = 121, + RISCV_REG_MCOUNTEREN = 122, + RISCV_REG_MSTATUSH = 123, + RISCV_REG_MUCOUNTEREN = 124, + RISCV_REG_MSCOUNTEREN = 125, + RISCV_REG_MHCOUNTEREN = 126, + RISCV_REG_MSCRATCH = 127, + RISCV_REG_MEPC = 128, + RISCV_REG_MCAUSE = 129, + RISCV_REG_MTVAL = 130, + RISCV_REG_MIP = 131, + RISCV_REG_MBADADDR = 132, + RISCV_REG_SSTATUS = 133, + RISCV_REG_SEDELEG = 134, + RISCV_REG_SIDELEG = 135, + RISCV_REG_SIE = 136, + RISCV_REG_STVEC = 137, + RISCV_REG_SCOUNTEREN = 138, + RISCV_REG_SSCRATCH = 139, + RISCV_REG_SEPC = 140, + RISCV_REG_SCAUSE = 141, + RISCV_REG_STVAL = 142, + RISCV_REG_SIP = 143, + RISCV_REG_SBADADDR = 144, + RISCV_REG_SPTBR = 145, + RISCV_REG_SATP = 146, + RISCV_REG_HSTATUS = 147, + RISCV_REG_HEDELEG = 148, + RISCV_REG_HIDELEG = 149, + RISCV_REG_HIE = 150, + RISCV_REG_HCOUNTEREN = 151, + RISCV_REG_HTVAL = 152, + RISCV_REG_HIP = 153, + RISCV_REG_HTINST = 154, + RISCV_REG_HGATP = 155, + RISCV_REG_HTIMEDELTA = 156, + RISCV_REG_HTIMEDELTAH = 157, + +// Floating-point registers + RISCV_REG_F0 = 158, + RISCV_REG_F1 = 159, + RISCV_REG_F2 = 160, + RISCV_REG_F3 = 161, + RISCV_REG_F4 = 162, + RISCV_REG_F5 = 163, + RISCV_REG_F6 = 164, + RISCV_REG_F7 = 165, + RISCV_REG_F8 = 166, + RISCV_REG_F9 = 167, + RISCV_REG_F10 = 168, + RISCV_REG_F11 = 169, + RISCV_REG_F12 = 170, + RISCV_REG_F13 = 171, + RISCV_REG_F14 = 172, + RISCV_REG_F15 = 173, + RISCV_REG_F16 = 174, + RISCV_REG_F17 = 175, + RISCV_REG_F18 = 176, + RISCV_REG_F19 = 177, + RISCV_REG_F20 = 178, + RISCV_REG_F21 = 179, + RISCV_REG_F22 = 180, + RISCV_REG_F23 = 181, + RISCV_REG_F24 = 182, + RISCV_REG_F25 = 183, + RISCV_REG_F26 = 184, + RISCV_REG_F27 = 185, + RISCV_REG_F28 = 186, + RISCV_REG_F29 = 187, + RISCV_REG_F30 = 188, + RISCV_REG_F31 = 189, + RISCV_REG_PC = 190, + RISCV_REG_ENDING = 191, + +// Alias registers + RISCV_REG_ZERO = 1, + RISCV_REG_RA = 2, + RISCV_REG_SP = 3, + RISCV_REG_GP = 4, + RISCV_REG_TP = 5, + RISCV_REG_T0 = 6, + RISCV_REG_T1 = 7, + RISCV_REG_T2 = 8, + RISCV_REG_S0 = 9, + RISCV_REG_FP = 9, + RISCV_REG_S1 = 10, + RISCV_REG_A0 = 11, + RISCV_REG_A1 = 12, + RISCV_REG_A2 = 13, + RISCV_REG_A3 = 14, + RISCV_REG_A4 = 15, + RISCV_REG_A5 = 16, + RISCV_REG_A6 = 17, + RISCV_REG_A7 = 18, + RISCV_REG_S2 = 19, + RISCV_REG_S3 = 20, + RISCV_REG_S4 = 21, + RISCV_REG_S5 = 22, + RISCV_REG_S6 = 23, + RISCV_REG_S7 = 24, + RISCV_REG_S8 = 25, + RISCV_REG_S9 = 26, + RISCV_REG_S10 = 27, + RISCV_REG_S11 = 28, + RISCV_REG_T3 = 29, + RISCV_REG_T4 = 30, + RISCV_REG_T5 = 31, + RISCV_REG_T6 = 32, + RISCV_REG_FT0 = 158, + RISCV_REG_FT1 = 159, + RISCV_REG_FT2 = 160, + RISCV_REG_FT3 = 161, + RISCV_REG_FT4 = 162, + RISCV_REG_FT5 = 163, + RISCV_REG_FT6 = 164, + RISCV_REG_FT7 = 165, + RISCV_REG_FS0 = 166, + RISCV_REG_FS1 = 167, + RISCV_REG_FA0 = 168, + RISCV_REG_FA1 = 169, + RISCV_REG_FA2 = 170, + RISCV_REG_FA3 = 171, + RISCV_REG_FA4 = 172, + RISCV_REG_FA5 = 173, + RISCV_REG_FA6 = 174, + RISCV_REG_FA7 = 175, + RISCV_REG_FS2 = 176, + RISCV_REG_FS3 = 177, + RISCV_REG_FS4 = 178, + RISCV_REG_FS5 = 179, + RISCV_REG_FS6 = 180, + RISCV_REG_FS7 = 181, + RISCV_REG_FS8 = 182, + RISCV_REG_FS9 = 183, + RISCV_REG_FS10 = 184, + RISCV_REG_FS11 = 185, + RISCV_REG_FT8 = 186, + RISCV_REG_FT9 = 187, + RISCV_REG_FT10 = 188, + RISCV_REG_FT11 = 189, + +}; diff --git a/bindings/zig/unicorn/s390x_const.zig b/bindings/zig/unicorn/s390x_const.zig new file mode 100644 index 00000000..9b1908b1 --- /dev/null +++ b/bindings/zig/unicorn/s390x_const.zig @@ -0,0 +1,126 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const s390xConst = enum(c_int) { + +// S390X CPU + + CPU_S390X_Z900 = 0, + CPU_S390X_Z900_2 = 1, + CPU_S390X_Z900_3 = 2, + CPU_S390X_Z800 = 3, + CPU_S390X_Z990 = 4, + CPU_S390X_Z990_2 = 5, + CPU_S390X_Z990_3 = 6, + CPU_S390X_Z890 = 7, + CPU_S390X_Z990_4 = 8, + CPU_S390X_Z890_2 = 9, + CPU_S390X_Z990_5 = 10, + CPU_S390X_Z890_3 = 11, + CPU_S390X_Z9EC = 12, + CPU_S390X_Z9EC_2 = 13, + CPU_S390X_Z9BC = 14, + CPU_S390X_Z9EC_3 = 15, + CPU_S390X_Z9BC_2 = 16, + CPU_S390X_Z10EC = 17, + CPU_S390X_Z10EC_2 = 18, + CPU_S390X_Z10BC = 19, + CPU_S390X_Z10EC_3 = 20, + CPU_S390X_Z10BC_2 = 21, + CPU_S390X_Z196 = 22, + CPU_S390X_Z196_2 = 23, + CPU_S390X_Z114 = 24, + CPU_S390X_ZEC12 = 25, + CPU_S390X_ZEC12_2 = 26, + CPU_S390X_ZBC12 = 27, + CPU_S390X_Z13 = 28, + CPU_S390X_Z13_2 = 29, + CPU_S390X_Z13S = 30, + CPU_S390X_Z14 = 31, + CPU_S390X_Z14_2 = 32, + CPU_S390X_Z14ZR1 = 33, + CPU_S390X_GEN15A = 34, + CPU_S390X_GEN15B = 35, + CPU_S390X_QEMU = 36, + CPU_S390X_MAX = 37, + CPU_S390X_ENDING = 38, + +// S390X registers + + S390X_REG_INVALID = 0, + +// General purpose registers + S390X_REG_R0 = 1, + S390X_REG_R1 = 2, + S390X_REG_R2 = 3, + S390X_REG_R3 = 4, + S390X_REG_R4 = 5, + S390X_REG_R5 = 6, + S390X_REG_R6 = 7, + S390X_REG_R7 = 8, + S390X_REG_R8 = 9, + S390X_REG_R9 = 10, + S390X_REG_R10 = 11, + S390X_REG_R11 = 12, + S390X_REG_R12 = 13, + S390X_REG_R13 = 14, + S390X_REG_R14 = 15, + S390X_REG_R15 = 16, + +// Floating point registers + S390X_REG_F0 = 17, + S390X_REG_F1 = 18, + S390X_REG_F2 = 19, + S390X_REG_F3 = 20, + S390X_REG_F4 = 21, + S390X_REG_F5 = 22, + S390X_REG_F6 = 23, + S390X_REG_F7 = 24, + S390X_REG_F8 = 25, + S390X_REG_F9 = 26, + S390X_REG_F10 = 27, + S390X_REG_F11 = 28, + S390X_REG_F12 = 29, + S390X_REG_F13 = 30, + S390X_REG_F14 = 31, + S390X_REG_F15 = 32, + S390X_REG_F16 = 33, + S390X_REG_F17 = 34, + S390X_REG_F18 = 35, + S390X_REG_F19 = 36, + S390X_REG_F20 = 37, + S390X_REG_F21 = 38, + S390X_REG_F22 = 39, + S390X_REG_F23 = 40, + S390X_REG_F24 = 41, + S390X_REG_F25 = 42, + S390X_REG_F26 = 43, + S390X_REG_F27 = 44, + S390X_REG_F28 = 45, + S390X_REG_F29 = 46, + S390X_REG_F30 = 47, + S390X_REG_F31 = 48, + +// Access registers + S390X_REG_A0 = 49, + S390X_REG_A1 = 50, + S390X_REG_A2 = 51, + S390X_REG_A3 = 52, + S390X_REG_A4 = 53, + S390X_REG_A5 = 54, + S390X_REG_A6 = 55, + S390X_REG_A7 = 56, + S390X_REG_A8 = 57, + S390X_REG_A9 = 58, + S390X_REG_A10 = 59, + S390X_REG_A11 = 60, + S390X_REG_A12 = 61, + S390X_REG_A13 = 62, + S390X_REG_A14 = 63, + S390X_REG_A15 = 64, + S390X_REG_PC = 65, + S390X_REG_PSWM = 66, + S390X_REG_ENDING = 67, + +// Alias registers + +}; diff --git a/bindings/zig/unicorn/sparc_const.zig b/bindings/zig/unicorn/sparc_const.zig new file mode 100644 index 00000000..f745e84f --- /dev/null +++ b/bindings/zig/unicorn/sparc_const.zig @@ -0,0 +1,138 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const sparcConst = enum(c_int) { + +// SPARC32 CPU + + CPU_SPARC32_FUJITSU_MB86904 = 0, + CPU_SPARC32_FUJITSU_MB86907 = 1, + CPU_SPARC32_TI_MICROSPARC_I = 2, + CPU_SPARC32_TI_MICROSPARC_II = 3, + CPU_SPARC32_TI_MICROSPARC_IIEP = 4, + CPU_SPARC32_TI_SUPERSPARC_40 = 5, + CPU_SPARC32_TI_SUPERSPARC_50 = 6, + CPU_SPARC32_TI_SUPERSPARC_51 = 7, + CPU_SPARC32_TI_SUPERSPARC_60 = 8, + CPU_SPARC32_TI_SUPERSPARC_61 = 9, + CPU_SPARC32_TI_SUPERSPARC_II = 10, + CPU_SPARC32_LEON2 = 11, + CPU_SPARC32_LEON3 = 12, + CPU_SPARC32_ENDING = 13, + +// SPARC64 CPU + + CPU_SPARC64_FUJITSU = 0, + CPU_SPARC64_FUJITSU_III = 1, + CPU_SPARC64_FUJITSU_IV = 2, + CPU_SPARC64_FUJITSU_V = 3, + CPU_SPARC64_TI_ULTRASPARC_I = 4, + CPU_SPARC64_TI_ULTRASPARC_II = 5, + CPU_SPARC64_TI_ULTRASPARC_III = 6, + CPU_SPARC64_TI_ULTRASPARC_IIE = 7, + CPU_SPARC64_SUN_ULTRASPARC_III = 8, + CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9, + CPU_SPARC64_SUN_ULTRASPARC_IIII = 10, + CPU_SPARC64_SUN_ULTRASPARC_IV = 11, + CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12, + CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13, + CPU_SPARC64_SUN_ULTRASPARC_T1 = 14, + CPU_SPARC64_SUN_ULTRASPARC_T2 = 15, + CPU_SPARC64_NEC_ULTRASPARC_I = 16, + CPU_SPARC64_ENDING = 17, + +// SPARC registers + + SPARC_REG_INVALID = 0, + SPARC_REG_F0 = 1, + SPARC_REG_F1 = 2, + SPARC_REG_F2 = 3, + SPARC_REG_F3 = 4, + SPARC_REG_F4 = 5, + SPARC_REG_F5 = 6, + SPARC_REG_F6 = 7, + SPARC_REG_F7 = 8, + SPARC_REG_F8 = 9, + SPARC_REG_F9 = 10, + SPARC_REG_F10 = 11, + SPARC_REG_F11 = 12, + SPARC_REG_F12 = 13, + SPARC_REG_F13 = 14, + SPARC_REG_F14 = 15, + SPARC_REG_F15 = 16, + SPARC_REG_F16 = 17, + SPARC_REG_F17 = 18, + SPARC_REG_F18 = 19, + SPARC_REG_F19 = 20, + SPARC_REG_F20 = 21, + SPARC_REG_F21 = 22, + SPARC_REG_F22 = 23, + SPARC_REG_F23 = 24, + SPARC_REG_F24 = 25, + SPARC_REG_F25 = 26, + SPARC_REG_F26 = 27, + SPARC_REG_F27 = 28, + SPARC_REG_F28 = 29, + SPARC_REG_F29 = 30, + SPARC_REG_F30 = 31, + SPARC_REG_F31 = 32, + SPARC_REG_F32 = 33, + SPARC_REG_F34 = 34, + SPARC_REG_F36 = 35, + SPARC_REG_F38 = 36, + SPARC_REG_F40 = 37, + SPARC_REG_F42 = 38, + SPARC_REG_F44 = 39, + SPARC_REG_F46 = 40, + SPARC_REG_F48 = 41, + SPARC_REG_F50 = 42, + SPARC_REG_F52 = 43, + SPARC_REG_F54 = 44, + SPARC_REG_F56 = 45, + SPARC_REG_F58 = 46, + SPARC_REG_F60 = 47, + SPARC_REG_F62 = 48, + SPARC_REG_FCC0 = 49, + SPARC_REG_FCC1 = 50, + SPARC_REG_FCC2 = 51, + SPARC_REG_FCC3 = 52, + SPARC_REG_G0 = 53, + SPARC_REG_G1 = 54, + SPARC_REG_G2 = 55, + SPARC_REG_G3 = 56, + SPARC_REG_G4 = 57, + SPARC_REG_G5 = 58, + SPARC_REG_G6 = 59, + SPARC_REG_G7 = 60, + SPARC_REG_I0 = 61, + SPARC_REG_I1 = 62, + SPARC_REG_I2 = 63, + SPARC_REG_I3 = 64, + SPARC_REG_I4 = 65, + SPARC_REG_I5 = 66, + SPARC_REG_FP = 67, + SPARC_REG_I7 = 68, + SPARC_REG_ICC = 69, + SPARC_REG_L0 = 70, + SPARC_REG_L1 = 71, + SPARC_REG_L2 = 72, + SPARC_REG_L3 = 73, + SPARC_REG_L4 = 74, + SPARC_REG_L5 = 75, + SPARC_REG_L6 = 76, + SPARC_REG_L7 = 77, + SPARC_REG_O0 = 78, + SPARC_REG_O1 = 79, + SPARC_REG_O2 = 80, + SPARC_REG_O3 = 81, + SPARC_REG_O4 = 82, + SPARC_REG_O5 = 83, + SPARC_REG_SP = 84, + SPARC_REG_O7 = 85, + SPARC_REG_Y = 86, + SPARC_REG_XCC = 87, + SPARC_REG_PC = 88, + SPARC_REG_ENDING = 89, + SPARC_REG_O6 = 84, + SPARC_REG_I6 = 67, + +}; diff --git a/bindings/zig/unicorn/tricore_const.zig b/bindings/zig/unicorn/tricore_const.zig new file mode 100644 index 00000000..9b51aea2 --- /dev/null +++ b/bindings/zig/unicorn/tricore_const.zig @@ -0,0 +1,128 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const tricoreConst = enum(c_int) { + +// TRICORE CPU + + CPU_TRICORE_TC1796 = 0, + CPU_TRICORE_TC1797 = 1, + CPU_TRICORE_TC27X = 2, + CPU_TRICORE_ENDING = 3, + +// TRICORE registers + + TRICORE_REG_INVALID = 0, + TRICORE_REG_A0 = 1, + TRICORE_REG_A1 = 2, + TRICORE_REG_A2 = 3, + TRICORE_REG_A3 = 4, + TRICORE_REG_A4 = 5, + TRICORE_REG_A5 = 6, + TRICORE_REG_A6 = 7, + TRICORE_REG_A7 = 8, + TRICORE_REG_A8 = 9, + TRICORE_REG_A9 = 10, + TRICORE_REG_A10 = 11, + TRICORE_REG_A11 = 12, + TRICORE_REG_A12 = 13, + TRICORE_REG_A13 = 14, + TRICORE_REG_A14 = 15, + TRICORE_REG_A15 = 16, + TRICORE_REG_D0 = 17, + TRICORE_REG_D1 = 18, + TRICORE_REG_D2 = 19, + TRICORE_REG_D3 = 20, + TRICORE_REG_D4 = 21, + TRICORE_REG_D5 = 22, + TRICORE_REG_D6 = 23, + TRICORE_REG_D7 = 24, + TRICORE_REG_D8 = 25, + TRICORE_REG_D9 = 26, + TRICORE_REG_D10 = 27, + TRICORE_REG_D11 = 28, + TRICORE_REG_D12 = 29, + TRICORE_REG_D13 = 30, + TRICORE_REG_D14 = 31, + TRICORE_REG_D15 = 32, + TRICORE_REG_PCXI = 33, + TRICORE_REG_PSW = 34, + TRICORE_REG_PSW_USB_C = 35, + TRICORE_REG_PSW_USB_V = 36, + TRICORE_REG_PSW_USB_SV = 37, + TRICORE_REG_PSW_USB_AV = 38, + TRICORE_REG_PSW_USB_SAV = 39, + TRICORE_REG_PC = 40, + TRICORE_REG_SYSCON = 41, + TRICORE_REG_CPU_ID = 42, + TRICORE_REG_BIV = 43, + TRICORE_REG_BTV = 44, + TRICORE_REG_ISP = 45, + TRICORE_REG_ICR = 46, + TRICORE_REG_FCX = 47, + TRICORE_REG_LCX = 48, + TRICORE_REG_COMPAT = 49, + TRICORE_REG_DPR0_U = 50, + TRICORE_REG_DPR1_U = 51, + TRICORE_REG_DPR2_U = 52, + TRICORE_REG_DPR3_U = 53, + TRICORE_REG_DPR0_L = 54, + TRICORE_REG_DPR1_L = 55, + TRICORE_REG_DPR2_L = 56, + TRICORE_REG_DPR3_L = 57, + TRICORE_REG_CPR0_U = 58, + TRICORE_REG_CPR1_U = 59, + TRICORE_REG_CPR2_U = 60, + TRICORE_REG_CPR3_U = 61, + TRICORE_REG_CPR0_L = 62, + TRICORE_REG_CPR1_L = 63, + TRICORE_REG_CPR2_L = 64, + TRICORE_REG_CPR3_L = 65, + TRICORE_REG_DPM0 = 66, + TRICORE_REG_DPM1 = 67, + TRICORE_REG_DPM2 = 68, + TRICORE_REG_DPM3 = 69, + TRICORE_REG_CPM0 = 70, + TRICORE_REG_CPM1 = 71, + TRICORE_REG_CPM2 = 72, + TRICORE_REG_CPM3 = 73, + TRICORE_REG_MMU_CON = 74, + TRICORE_REG_MMU_ASI = 75, + TRICORE_REG_MMU_TVA = 76, + TRICORE_REG_MMU_TPA = 77, + TRICORE_REG_MMU_TPX = 78, + TRICORE_REG_MMU_TFA = 79, + TRICORE_REG_BMACON = 80, + TRICORE_REG_SMACON = 81, + TRICORE_REG_DIEAR = 82, + TRICORE_REG_DIETR = 83, + TRICORE_REG_CCDIER = 84, + TRICORE_REG_MIECON = 85, + TRICORE_REG_PIEAR = 86, + TRICORE_REG_PIETR = 87, + TRICORE_REG_CCPIER = 88, + TRICORE_REG_DBGSR = 89, + TRICORE_REG_EXEVT = 90, + TRICORE_REG_CREVT = 91, + TRICORE_REG_SWEVT = 92, + TRICORE_REG_TR0EVT = 93, + TRICORE_REG_TR1EVT = 94, + TRICORE_REG_DMS = 95, + TRICORE_REG_DCX = 96, + TRICORE_REG_DBGTCR = 97, + TRICORE_REG_CCTRL = 98, + TRICORE_REG_CCNT = 99, + TRICORE_REG_ICNT = 100, + TRICORE_REG_M1CNT = 101, + TRICORE_REG_M2CNT = 102, + TRICORE_REG_M3CNT = 103, + TRICORE_REG_ENDING = 104, + TRICORE_REG_GA0 = 1, + TRICORE_REG_GA1 = 2, + TRICORE_REG_GA8 = 9, + TRICORE_REG_GA9 = 10, + TRICORE_REG_SP = 11, + TRICORE_REG_LR = 12, + TRICORE_REG_IA = 16, + TRICORE_REG_ID = 32, + +}; diff --git a/bindings/zig/unicorn/unicorn.zig b/bindings/zig/unicorn/unicorn.zig new file mode 100644 index 00000000..43d19738 --- /dev/null +++ b/bindings/zig/unicorn/unicorn.zig @@ -0,0 +1,13 @@ +// Architectures +pub const arm = @import("arm_const.zig"); +pub const arm64 = @import("arm64_const.zig"); +pub const m68k = @import("m68k_const.zig"); +pub const mips = @import("mips_const.zig"); +pub const ppc = @import("ppc_const.zig"); +pub const riscv = @import("riscv_const.zig"); +pub const tricore = @import("tricore_const.zig"); +pub const sparc = @import("sparc_const.zig"); +pub const s390x = @import("s390x_const.zig"); +pub const x86 = @import("x86_const.zig"); +// Unicorn +pub const unicorn = @import("unicorn_const.zig"); diff --git a/bindings/zig/unicorn/unicorn_const.zig b/bindings/zig/unicorn/unicorn_const.zig new file mode 100644 index 00000000..b7ccad62 --- /dev/null +++ b/bindings/zig/unicorn/unicorn_const.zig @@ -0,0 +1,144 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const unicornConst = enum(c_int) { + API_MAJOR = 2, + + API_MINOR = 0, + API_PATCH = 1, + API_EXTRA = 255, + VERSION_MAJOR = 2, + + VERSION_MINOR = 0, + VERSION_PATCH = 1, + VERSION_EXTRA = 255, + SECOND_SCALE = 1000000, + MILISECOND_SCALE = 1000, + ARCH_ARM = 1, + ARCH_ARM64 = 2, + ARCH_MIPS = 3, + ARCH_X86 = 4, + ARCH_PPC = 5, + ARCH_SPARC = 6, + ARCH_M68K = 7, + ARCH_RISCV = 8, + ARCH_S390X = 9, + ARCH_TRICORE = 10, + ARCH_MAX = 11, + + MODE_LITTLE_ENDIAN = 0, + MODE_BIG_ENDIAN = 1073741824, + + MODE_ARM = 0, + MODE_THUMB = 16, + MODE_MCLASS = 32, + MODE_V8 = 64, + MODE_ARMBE8 = 1024, + MODE_ARM926 = 128, + MODE_ARM946 = 256, + MODE_ARM1176 = 512, + MODE_MICRO = 16, + MODE_MIPS3 = 32, + MODE_MIPS32R6 = 64, + MODE_MIPS32 = 4, + MODE_MIPS64 = 8, + MODE_16 = 2, + MODE_32 = 4, + MODE_64 = 8, + MODE_PPC32 = 4, + MODE_PPC64 = 8, + MODE_QPX = 16, + MODE_SPARC32 = 4, + MODE_SPARC64 = 8, + MODE_V9 = 16, + MODE_RISCV32 = 4, + MODE_RISCV64 = 8, + + ERR_OK = 0, + ERR_NOMEM = 1, + ERR_ARCH = 2, + ERR_HANDLE = 3, + ERR_MODE = 4, + ERR_VERSION = 5, + ERR_READ_UNMAPPED = 6, + ERR_WRITE_UNMAPPED = 7, + ERR_FETCH_UNMAPPED = 8, + ERR_HOOK = 9, + ERR_INSN_INVALID = 10, + ERR_MAP = 11, + ERR_WRITE_PROT = 12, + ERR_READ_PROT = 13, + ERR_FETCH_PROT = 14, + ERR_ARG = 15, + ERR_READ_UNALIGNED = 16, + ERR_WRITE_UNALIGNED = 17, + ERR_FETCH_UNALIGNED = 18, + ERR_HOOK_EXIST = 19, + ERR_RESOURCE = 20, + ERR_EXCEPTION = 21, + MEM_READ = 16, + MEM_WRITE = 17, + MEM_FETCH = 18, + MEM_READ_UNMAPPED = 19, + MEM_WRITE_UNMAPPED = 20, + MEM_FETCH_UNMAPPED = 21, + MEM_WRITE_PROT = 22, + MEM_READ_PROT = 23, + MEM_FETCH_PROT = 24, + MEM_READ_AFTER = 25, + + TCG_OP_SUB = 0, + TCG_OP_FLAG_CMP = 1, + TCG_OP_FLAG_DIRECT = 2, + HOOK_INTR = 1, + HOOK_INSN = 2, + HOOK_CODE = 4, + HOOK_BLOCK = 8, + HOOK_MEM_READ_UNMAPPED = 16, + HOOK_MEM_WRITE_UNMAPPED = 32, + HOOK_MEM_FETCH_UNMAPPED = 64, + HOOK_MEM_READ_PROT = 128, + HOOK_MEM_WRITE_PROT = 256, + HOOK_MEM_FETCH_PROT = 512, + HOOK_MEM_READ = 1024, + HOOK_MEM_WRITE = 2048, + HOOK_MEM_FETCH = 4096, + HOOK_MEM_READ_AFTER = 8192, + HOOK_INSN_INVALID = 16384, + HOOK_EDGE_GENERATED = 32768, + HOOK_TCG_OPCODE = 65536, + HOOK_MEM_UNMAPPED = 112, + HOOK_MEM_PROT = 896, + HOOK_MEM_READ_INVALID = 144, + HOOK_MEM_WRITE_INVALID = 288, + HOOK_MEM_FETCH_INVALID = 576, + HOOK_MEM_INVALID = 1008, + HOOK_MEM_VALID = 7168, + QUERY_MODE = 1, + QUERY_PAGE_SIZE = 2, + QUERY_ARCH = 3, + QUERY_TIMEOUT = 4, + + CTL_IO_NONE = 0, + CTL_IO_WRITE = 1, + CTL_IO_READ = 2, + CTL_IO_READ_WRITE = 3, + + CTL_UC_MODE = 0, + CTL_UC_PAGE_SIZE = 1, + CTL_UC_ARCH = 2, + CTL_UC_TIMEOUT = 3, + CTL_UC_USE_EXITS = 4, + CTL_UC_EXITS_CNT = 5, + CTL_UC_EXITS = 6, + CTL_CPU_MODEL = 7, + CTL_TB_REQUEST_CACHE = 8, + CTL_TB_REMOVE_CACHE = 9, + CTL_TB_FLUSH = 10, + + PROT_NONE = 0, + PROT_READ = 1, + PROT_WRITE = 2, + PROT_EXEC = 4, + PROT_ALL = 7, + +}; diff --git a/bindings/zig/unicorn/x86_const.zig b/bindings/zig/unicorn/x86_const.zig new file mode 100644 index 00000000..b94f53a1 --- /dev/null +++ b/bindings/zig/unicorn/x86_const.zig @@ -0,0 +1,1632 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +pub const x86Const = enum(c_int) { + +// X86 CPU + + CPU_X86_QEMU64 = 0, + CPU_X86_PHENOM = 1, + CPU_X86_CORE2DUO = 2, + CPU_X86_KVM64 = 3, + CPU_X86_QEMU32 = 4, + CPU_X86_KVM32 = 5, + CPU_X86_COREDUO = 6, + CPU_X86_486 = 7, + CPU_X86_PENTIUM = 8, + CPU_X86_PENTIUM2 = 9, + CPU_X86_PENTIUM3 = 10, + CPU_X86_ATHLON = 11, + CPU_X86_N270 = 12, + CPU_X86_CONROE = 13, + CPU_X86_PENRYN = 14, + CPU_X86_NEHALEM = 15, + CPU_X86_WESTMERE = 16, + CPU_X86_SANDYBRIDGE = 17, + CPU_X86_IVYBRIDGE = 18, + CPU_X86_HASWELL = 19, + CPU_X86_BROADWELL = 20, + CPU_X86_SKYLAKE_CLIENT = 21, + CPU_X86_SKYLAKE_SERVER = 22, + CPU_X86_CASCADELAKE_SERVER = 23, + CPU_X86_COOPERLAKE = 24, + CPU_X86_ICELAKE_CLIENT = 25, + CPU_X86_ICELAKE_SERVER = 26, + CPU_X86_DENVERTON = 27, + CPU_X86_SNOWRIDGE = 28, + CPU_X86_KNIGHTSMILL = 29, + CPU_X86_OPTERON_G1 = 30, + CPU_X86_OPTERON_G2 = 31, + CPU_X86_OPTERON_G3 = 32, + CPU_X86_OPTERON_G4 = 33, + CPU_X86_OPTERON_G5 = 34, + CPU_X86_EPYC = 35, + CPU_X86_DHYANA = 36, + CPU_X86_EPYC_ROME = 37, + CPU_X86_ENDING = 38, + +// X86 registers + + X86_REG_INVALID = 0, + X86_REG_AH = 1, + X86_REG_AL = 2, + X86_REG_AX = 3, + X86_REG_BH = 4, + X86_REG_BL = 5, + X86_REG_BP = 6, + X86_REG_BPL = 7, + X86_REG_BX = 8, + X86_REG_CH = 9, + X86_REG_CL = 10, + X86_REG_CS = 11, + X86_REG_CX = 12, + X86_REG_DH = 13, + X86_REG_DI = 14, + X86_REG_DIL = 15, + X86_REG_DL = 16, + X86_REG_DS = 17, + X86_REG_DX = 18, + X86_REG_EAX = 19, + X86_REG_EBP = 20, + X86_REG_EBX = 21, + X86_REG_ECX = 22, + X86_REG_EDI = 23, + X86_REG_EDX = 24, + X86_REG_EFLAGS = 25, + X86_REG_EIP = 26, + X86_REG_ES = 28, + X86_REG_ESI = 29, + X86_REG_ESP = 30, + X86_REG_FPSW = 31, + X86_REG_FS = 32, + X86_REG_GS = 33, + X86_REG_IP = 34, + X86_REG_RAX = 35, + X86_REG_RBP = 36, + X86_REG_RBX = 37, + X86_REG_RCX = 38, + X86_REG_RDI = 39, + X86_REG_RDX = 40, + X86_REG_RIP = 41, + X86_REG_RSI = 43, + X86_REG_RSP = 44, + X86_REG_SI = 45, + X86_REG_SIL = 46, + X86_REG_SP = 47, + X86_REG_SPL = 48, + X86_REG_SS = 49, + X86_REG_CR0 = 50, + X86_REG_CR1 = 51, + X86_REG_CR2 = 52, + X86_REG_CR3 = 53, + X86_REG_CR4 = 54, + X86_REG_CR8 = 58, + X86_REG_DR0 = 66, + X86_REG_DR1 = 67, + X86_REG_DR2 = 68, + X86_REG_DR3 = 69, + X86_REG_DR4 = 70, + X86_REG_DR5 = 71, + X86_REG_DR6 = 72, + X86_REG_DR7 = 73, + X86_REG_FP0 = 82, + X86_REG_FP1 = 83, + X86_REG_FP2 = 84, + X86_REG_FP3 = 85, + X86_REG_FP4 = 86, + X86_REG_FP5 = 87, + X86_REG_FP6 = 88, + X86_REG_FP7 = 89, + X86_REG_K0 = 90, + X86_REG_K1 = 91, + X86_REG_K2 = 92, + X86_REG_K3 = 93, + X86_REG_K4 = 94, + X86_REG_K5 = 95, + X86_REG_K6 = 96, + X86_REG_K7 = 97, + X86_REG_MM0 = 98, + X86_REG_MM1 = 99, + X86_REG_MM2 = 100, + X86_REG_MM3 = 101, + X86_REG_MM4 = 102, + X86_REG_MM5 = 103, + X86_REG_MM6 = 104, + X86_REG_MM7 = 105, + X86_REG_R8 = 106, + X86_REG_R9 = 107, + X86_REG_R10 = 108, + X86_REG_R11 = 109, + X86_REG_R12 = 110, + X86_REG_R13 = 111, + X86_REG_R14 = 112, + X86_REG_R15 = 113, + X86_REG_ST0 = 114, + X86_REG_ST1 = 115, + X86_REG_ST2 = 116, + X86_REG_ST3 = 117, + X86_REG_ST4 = 118, + X86_REG_ST5 = 119, + X86_REG_ST6 = 120, + X86_REG_ST7 = 121, + X86_REG_XMM0 = 122, + X86_REG_XMM1 = 123, + X86_REG_XMM2 = 124, + X86_REG_XMM3 = 125, + X86_REG_XMM4 = 126, + X86_REG_XMM5 = 127, + X86_REG_XMM6 = 128, + X86_REG_XMM7 = 129, + X86_REG_XMM8 = 130, + X86_REG_XMM9 = 131, + X86_REG_XMM10 = 132, + X86_REG_XMM11 = 133, + X86_REG_XMM12 = 134, + X86_REG_XMM13 = 135, + X86_REG_XMM14 = 136, + X86_REG_XMM15 = 137, + X86_REG_XMM16 = 138, + X86_REG_XMM17 = 139, + X86_REG_XMM18 = 140, + X86_REG_XMM19 = 141, + X86_REG_XMM20 = 142, + X86_REG_XMM21 = 143, + X86_REG_XMM22 = 144, + X86_REG_XMM23 = 145, + X86_REG_XMM24 = 146, + X86_REG_XMM25 = 147, + X86_REG_XMM26 = 148, + X86_REG_XMM27 = 149, + X86_REG_XMM28 = 150, + X86_REG_XMM29 = 151, + X86_REG_XMM30 = 152, + X86_REG_XMM31 = 153, + X86_REG_YMM0 = 154, + X86_REG_YMM1 = 155, + X86_REG_YMM2 = 156, + X86_REG_YMM3 = 157, + X86_REG_YMM4 = 158, + X86_REG_YMM5 = 159, + X86_REG_YMM6 = 160, + X86_REG_YMM7 = 161, + X86_REG_YMM8 = 162, + X86_REG_YMM9 = 163, + X86_REG_YMM10 = 164, + X86_REG_YMM11 = 165, + X86_REG_YMM12 = 166, + X86_REG_YMM13 = 167, + X86_REG_YMM14 = 168, + X86_REG_YMM15 = 169, + X86_REG_YMM16 = 170, + X86_REG_YMM17 = 171, + X86_REG_YMM18 = 172, + X86_REG_YMM19 = 173, + X86_REG_YMM20 = 174, + X86_REG_YMM21 = 175, + X86_REG_YMM22 = 176, + X86_REG_YMM23 = 177, + X86_REG_YMM24 = 178, + X86_REG_YMM25 = 179, + X86_REG_YMM26 = 180, + X86_REG_YMM27 = 181, + X86_REG_YMM28 = 182, + X86_REG_YMM29 = 183, + X86_REG_YMM30 = 184, + X86_REG_YMM31 = 185, + X86_REG_ZMM0 = 186, + X86_REG_ZMM1 = 187, + X86_REG_ZMM2 = 188, + X86_REG_ZMM3 = 189, + X86_REG_ZMM4 = 190, + X86_REG_ZMM5 = 191, + X86_REG_ZMM6 = 192, + X86_REG_ZMM7 = 193, + X86_REG_ZMM8 = 194, + X86_REG_ZMM9 = 195, + X86_REG_ZMM10 = 196, + X86_REG_ZMM11 = 197, + X86_REG_ZMM12 = 198, + X86_REG_ZMM13 = 199, + X86_REG_ZMM14 = 200, + X86_REG_ZMM15 = 201, + X86_REG_ZMM16 = 202, + X86_REG_ZMM17 = 203, + X86_REG_ZMM18 = 204, + X86_REG_ZMM19 = 205, + X86_REG_ZMM20 = 206, + X86_REG_ZMM21 = 207, + X86_REG_ZMM22 = 208, + X86_REG_ZMM23 = 209, + X86_REG_ZMM24 = 210, + X86_REG_ZMM25 = 211, + X86_REG_ZMM26 = 212, + X86_REG_ZMM27 = 213, + X86_REG_ZMM28 = 214, + X86_REG_ZMM29 = 215, + X86_REG_ZMM30 = 216, + X86_REG_ZMM31 = 217, + X86_REG_R8B = 218, + X86_REG_R9B = 219, + X86_REG_R10B = 220, + X86_REG_R11B = 221, + X86_REG_R12B = 222, + X86_REG_R13B = 223, + X86_REG_R14B = 224, + X86_REG_R15B = 225, + X86_REG_R8D = 226, + X86_REG_R9D = 227, + X86_REG_R10D = 228, + X86_REG_R11D = 229, + X86_REG_R12D = 230, + X86_REG_R13D = 231, + X86_REG_R14D = 232, + X86_REG_R15D = 233, + X86_REG_R8W = 234, + X86_REG_R9W = 235, + X86_REG_R10W = 236, + X86_REG_R11W = 237, + X86_REG_R12W = 238, + X86_REG_R13W = 239, + X86_REG_R14W = 240, + X86_REG_R15W = 241, + X86_REG_IDTR = 242, + X86_REG_GDTR = 243, + X86_REG_LDTR = 244, + X86_REG_TR = 245, + X86_REG_FPCW = 246, + X86_REG_FPTAG = 247, + X86_REG_MSR = 248, + X86_REG_MXCSR = 249, + X86_REG_FS_BASE = 250, + X86_REG_GS_BASE = 251, + X86_REG_FLAGS = 252, + X86_REG_RFLAGS = 253, + X86_REG_FIP = 254, + X86_REG_FCS = 255, + X86_REG_FDP = 256, + X86_REG_FDS = 257, + X86_REG_FOP = 258, + X86_REG_ENDING = 259, + +// X86 instructions + + X86_INS_INVALID = 0, + X86_INS_AAA = 1, + X86_INS_AAD = 2, + X86_INS_AAM = 3, + X86_INS_AAS = 4, + X86_INS_FABS = 5, + X86_INS_ADC = 6, + X86_INS_ADCX = 7, + X86_INS_ADD = 8, + X86_INS_ADDPD = 9, + X86_INS_ADDPS = 10, + X86_INS_ADDSD = 11, + X86_INS_ADDSS = 12, + X86_INS_ADDSUBPD = 13, + X86_INS_ADDSUBPS = 14, + X86_INS_FADD = 15, + X86_INS_FIADD = 16, + X86_INS_FADDP = 17, + X86_INS_ADOX = 18, + X86_INS_AESDECLAST = 19, + X86_INS_AESDEC = 20, + X86_INS_AESENCLAST = 21, + X86_INS_AESENC = 22, + X86_INS_AESIMC = 23, + X86_INS_AESKEYGENASSIST = 24, + X86_INS_AND = 25, + X86_INS_ANDN = 26, + X86_INS_ANDNPD = 27, + X86_INS_ANDNPS = 28, + X86_INS_ANDPD = 29, + X86_INS_ANDPS = 30, + X86_INS_ARPL = 31, + X86_INS_BEXTR = 32, + X86_INS_BLCFILL = 33, + X86_INS_BLCI = 34, + X86_INS_BLCIC = 35, + X86_INS_BLCMSK = 36, + X86_INS_BLCS = 37, + X86_INS_BLENDPD = 38, + X86_INS_BLENDPS = 39, + X86_INS_BLENDVPD = 40, + X86_INS_BLENDVPS = 41, + X86_INS_BLSFILL = 42, + X86_INS_BLSI = 43, + X86_INS_BLSIC = 44, + X86_INS_BLSMSK = 45, + X86_INS_BLSR = 46, + X86_INS_BOUND = 47, + X86_INS_BSF = 48, + X86_INS_BSR = 49, + X86_INS_BSWAP = 50, + X86_INS_BT = 51, + X86_INS_BTC = 52, + X86_INS_BTR = 53, + X86_INS_BTS = 54, + X86_INS_BZHI = 55, + X86_INS_CALL = 56, + X86_INS_CBW = 57, + X86_INS_CDQ = 58, + X86_INS_CDQE = 59, + X86_INS_FCHS = 60, + X86_INS_CLAC = 61, + X86_INS_CLC = 62, + X86_INS_CLD = 63, + X86_INS_CLFLUSH = 64, + X86_INS_CLFLUSHOPT = 65, + X86_INS_CLGI = 66, + X86_INS_CLI = 67, + X86_INS_CLTS = 68, + X86_INS_CLWB = 69, + X86_INS_CMC = 70, + X86_INS_CMOVA = 71, + X86_INS_CMOVAE = 72, + X86_INS_CMOVB = 73, + X86_INS_CMOVBE = 74, + X86_INS_FCMOVBE = 75, + X86_INS_FCMOVB = 76, + X86_INS_CMOVE = 77, + X86_INS_FCMOVE = 78, + X86_INS_CMOVG = 79, + X86_INS_CMOVGE = 80, + X86_INS_CMOVL = 81, + X86_INS_CMOVLE = 82, + X86_INS_FCMOVNBE = 83, + X86_INS_FCMOVNB = 84, + X86_INS_CMOVNE = 85, + X86_INS_FCMOVNE = 86, + X86_INS_CMOVNO = 87, + X86_INS_CMOVNP = 88, + X86_INS_FCMOVNU = 89, + X86_INS_CMOVNS = 90, + X86_INS_CMOVO = 91, + X86_INS_CMOVP = 92, + X86_INS_FCMOVU = 93, + X86_INS_CMOVS = 94, + X86_INS_CMP = 95, + X86_INS_CMPPD = 96, + X86_INS_CMPPS = 97, + X86_INS_CMPSB = 98, + X86_INS_CMPSD = 99, + X86_INS_CMPSQ = 100, + X86_INS_CMPSS = 101, + X86_INS_CMPSW = 102, + X86_INS_CMPXCHG16B = 103, + X86_INS_CMPXCHG = 104, + X86_INS_CMPXCHG8B = 105, + X86_INS_COMISD = 106, + X86_INS_COMISS = 107, + X86_INS_FCOMP = 108, + X86_INS_FCOMPI = 109, + X86_INS_FCOMI = 110, + X86_INS_FCOM = 111, + X86_INS_FCOS = 112, + X86_INS_CPUID = 113, + X86_INS_CQO = 114, + X86_INS_CRC32 = 115, + X86_INS_CVTDQ2PD = 116, + X86_INS_CVTDQ2PS = 117, + X86_INS_CVTPD2DQ = 118, + X86_INS_CVTPD2PS = 119, + X86_INS_CVTPS2DQ = 120, + X86_INS_CVTPS2PD = 121, + X86_INS_CVTSD2SI = 122, + X86_INS_CVTSD2SS = 123, + X86_INS_CVTSI2SD = 124, + X86_INS_CVTSI2SS = 125, + X86_INS_CVTSS2SD = 126, + X86_INS_CVTSS2SI = 127, + X86_INS_CVTTPD2DQ = 128, + X86_INS_CVTTPS2DQ = 129, + X86_INS_CVTTSD2SI = 130, + X86_INS_CVTTSS2SI = 131, + X86_INS_CWD = 132, + X86_INS_CWDE = 133, + X86_INS_DAA = 134, + X86_INS_DAS = 135, + X86_INS_DATA16 = 136, + X86_INS_DEC = 137, + X86_INS_DIV = 138, + X86_INS_DIVPD = 139, + X86_INS_DIVPS = 140, + X86_INS_FDIVR = 141, + X86_INS_FIDIVR = 142, + X86_INS_FDIVRP = 143, + X86_INS_DIVSD = 144, + X86_INS_DIVSS = 145, + X86_INS_FDIV = 146, + X86_INS_FIDIV = 147, + X86_INS_FDIVP = 148, + X86_INS_DPPD = 149, + X86_INS_DPPS = 150, + X86_INS_RET = 151, + X86_INS_ENCLS = 152, + X86_INS_ENCLU = 153, + X86_INS_ENTER = 154, + X86_INS_EXTRACTPS = 155, + X86_INS_EXTRQ = 156, + X86_INS_F2XM1 = 157, + X86_INS_LCALL = 158, + X86_INS_LJMP = 159, + X86_INS_FBLD = 160, + X86_INS_FBSTP = 161, + X86_INS_FCOMPP = 162, + X86_INS_FDECSTP = 163, + X86_INS_FEMMS = 164, + X86_INS_FFREE = 165, + X86_INS_FICOM = 166, + X86_INS_FICOMP = 167, + X86_INS_FINCSTP = 168, + X86_INS_FLDCW = 169, + X86_INS_FLDENV = 170, + X86_INS_FLDL2E = 171, + X86_INS_FLDL2T = 172, + X86_INS_FLDLG2 = 173, + X86_INS_FLDLN2 = 174, + X86_INS_FLDPI = 175, + X86_INS_FNCLEX = 176, + X86_INS_FNINIT = 177, + X86_INS_FNOP = 178, + X86_INS_FNSTCW = 179, + X86_INS_FNSTSW = 180, + X86_INS_FPATAN = 181, + X86_INS_FPREM = 182, + X86_INS_FPREM1 = 183, + X86_INS_FPTAN = 184, + X86_INS_FFREEP = 185, + X86_INS_FRNDINT = 186, + X86_INS_FRSTOR = 187, + X86_INS_FNSAVE = 188, + X86_INS_FSCALE = 189, + X86_INS_FSETPM = 190, + X86_INS_FSINCOS = 191, + X86_INS_FNSTENV = 192, + X86_INS_FXAM = 193, + X86_INS_FXRSTOR = 194, + X86_INS_FXRSTOR64 = 195, + X86_INS_FXSAVE = 196, + X86_INS_FXSAVE64 = 197, + X86_INS_FXTRACT = 198, + X86_INS_FYL2X = 199, + X86_INS_FYL2XP1 = 200, + X86_INS_MOVAPD = 201, + X86_INS_MOVAPS = 202, + X86_INS_ORPD = 203, + X86_INS_ORPS = 204, + X86_INS_VMOVAPD = 205, + X86_INS_VMOVAPS = 206, + X86_INS_XORPD = 207, + X86_INS_XORPS = 208, + X86_INS_GETSEC = 209, + X86_INS_HADDPD = 210, + X86_INS_HADDPS = 211, + X86_INS_HLT = 212, + X86_INS_HSUBPD = 213, + X86_INS_HSUBPS = 214, + X86_INS_IDIV = 215, + X86_INS_FILD = 216, + X86_INS_IMUL = 217, + X86_INS_IN = 218, + X86_INS_INC = 219, + X86_INS_INSB = 220, + X86_INS_INSERTPS = 221, + X86_INS_INSERTQ = 222, + X86_INS_INSD = 223, + X86_INS_INSW = 224, + X86_INS_INT = 225, + X86_INS_INT1 = 226, + X86_INS_INT3 = 227, + X86_INS_INTO = 228, + X86_INS_INVD = 229, + X86_INS_INVEPT = 230, + X86_INS_INVLPG = 231, + X86_INS_INVLPGA = 232, + X86_INS_INVPCID = 233, + X86_INS_INVVPID = 234, + X86_INS_IRET = 235, + X86_INS_IRETD = 236, + X86_INS_IRETQ = 237, + X86_INS_FISTTP = 238, + X86_INS_FIST = 239, + X86_INS_FISTP = 240, + X86_INS_UCOMISD = 241, + X86_INS_UCOMISS = 242, + X86_INS_VCOMISD = 243, + X86_INS_VCOMISS = 244, + X86_INS_VCVTSD2SS = 245, + X86_INS_VCVTSI2SD = 246, + X86_INS_VCVTSI2SS = 247, + X86_INS_VCVTSS2SD = 248, + X86_INS_VCVTTSD2SI = 249, + X86_INS_VCVTTSD2USI = 250, + X86_INS_VCVTTSS2SI = 251, + X86_INS_VCVTTSS2USI = 252, + X86_INS_VCVTUSI2SD = 253, + X86_INS_VCVTUSI2SS = 254, + X86_INS_VUCOMISD = 255, + X86_INS_VUCOMISS = 256, + X86_INS_JAE = 257, + X86_INS_JA = 258, + X86_INS_JBE = 259, + X86_INS_JB = 260, + X86_INS_JCXZ = 261, + X86_INS_JECXZ = 262, + X86_INS_JE = 263, + X86_INS_JGE = 264, + X86_INS_JG = 265, + X86_INS_JLE = 266, + X86_INS_JL = 267, + X86_INS_JMP = 268, + X86_INS_JNE = 269, + X86_INS_JNO = 270, + X86_INS_JNP = 271, + X86_INS_JNS = 272, + X86_INS_JO = 273, + X86_INS_JP = 274, + X86_INS_JRCXZ = 275, + X86_INS_JS = 276, + X86_INS_KANDB = 277, + X86_INS_KANDD = 278, + X86_INS_KANDNB = 279, + X86_INS_KANDND = 280, + X86_INS_KANDNQ = 281, + X86_INS_KANDNW = 282, + X86_INS_KANDQ = 283, + X86_INS_KANDW = 284, + X86_INS_KMOVB = 285, + X86_INS_KMOVD = 286, + X86_INS_KMOVQ = 287, + X86_INS_KMOVW = 288, + X86_INS_KNOTB = 289, + X86_INS_KNOTD = 290, + X86_INS_KNOTQ = 291, + X86_INS_KNOTW = 292, + X86_INS_KORB = 293, + X86_INS_KORD = 294, + X86_INS_KORQ = 295, + X86_INS_KORTESTB = 296, + X86_INS_KORTESTD = 297, + X86_INS_KORTESTQ = 298, + X86_INS_KORTESTW = 299, + X86_INS_KORW = 300, + X86_INS_KSHIFTLB = 301, + X86_INS_KSHIFTLD = 302, + X86_INS_KSHIFTLQ = 303, + X86_INS_KSHIFTLW = 304, + X86_INS_KSHIFTRB = 305, + X86_INS_KSHIFTRD = 306, + X86_INS_KSHIFTRQ = 307, + X86_INS_KSHIFTRW = 308, + X86_INS_KUNPCKBW = 309, + X86_INS_KXNORB = 310, + X86_INS_KXNORD = 311, + X86_INS_KXNORQ = 312, + X86_INS_KXNORW = 313, + X86_INS_KXORB = 314, + X86_INS_KXORD = 315, + X86_INS_KXORQ = 316, + X86_INS_KXORW = 317, + X86_INS_LAHF = 318, + X86_INS_LAR = 319, + X86_INS_LDDQU = 320, + X86_INS_LDMXCSR = 321, + X86_INS_LDS = 322, + X86_INS_FLDZ = 323, + X86_INS_FLD1 = 324, + X86_INS_FLD = 325, + X86_INS_LEA = 326, + X86_INS_LEAVE = 327, + X86_INS_LES = 328, + X86_INS_LFENCE = 329, + X86_INS_LFS = 330, + X86_INS_LGDT = 331, + X86_INS_LGS = 332, + X86_INS_LIDT = 333, + X86_INS_LLDT = 334, + X86_INS_LMSW = 335, + X86_INS_OR = 336, + X86_INS_SUB = 337, + X86_INS_XOR = 338, + X86_INS_LODSB = 339, + X86_INS_LODSD = 340, + X86_INS_LODSQ = 341, + X86_INS_LODSW = 342, + X86_INS_LOOP = 343, + X86_INS_LOOPE = 344, + X86_INS_LOOPNE = 345, + X86_INS_RETF = 346, + X86_INS_RETFQ = 347, + X86_INS_LSL = 348, + X86_INS_LSS = 349, + X86_INS_LTR = 350, + X86_INS_XADD = 351, + X86_INS_LZCNT = 352, + X86_INS_MASKMOVDQU = 353, + X86_INS_MAXPD = 354, + X86_INS_MAXPS = 355, + X86_INS_MAXSD = 356, + X86_INS_MAXSS = 357, + X86_INS_MFENCE = 358, + X86_INS_MINPD = 359, + X86_INS_MINPS = 360, + X86_INS_MINSD = 361, + X86_INS_MINSS = 362, + X86_INS_CVTPD2PI = 363, + X86_INS_CVTPI2PD = 364, + X86_INS_CVTPI2PS = 365, + X86_INS_CVTPS2PI = 366, + X86_INS_CVTTPD2PI = 367, + X86_INS_CVTTPS2PI = 368, + X86_INS_EMMS = 369, + X86_INS_MASKMOVQ = 370, + X86_INS_MOVD = 371, + X86_INS_MOVDQ2Q = 372, + X86_INS_MOVNTQ = 373, + X86_INS_MOVQ2DQ = 374, + X86_INS_MOVQ = 375, + X86_INS_PABSB = 376, + X86_INS_PABSD = 377, + X86_INS_PABSW = 378, + X86_INS_PACKSSDW = 379, + X86_INS_PACKSSWB = 380, + X86_INS_PACKUSWB = 381, + X86_INS_PADDB = 382, + X86_INS_PADDD = 383, + X86_INS_PADDQ = 384, + X86_INS_PADDSB = 385, + X86_INS_PADDSW = 386, + X86_INS_PADDUSB = 387, + X86_INS_PADDUSW = 388, + X86_INS_PADDW = 389, + X86_INS_PALIGNR = 390, + X86_INS_PANDN = 391, + X86_INS_PAND = 392, + X86_INS_PAVGB = 393, + X86_INS_PAVGW = 394, + X86_INS_PCMPEQB = 395, + X86_INS_PCMPEQD = 396, + X86_INS_PCMPEQW = 397, + X86_INS_PCMPGTB = 398, + X86_INS_PCMPGTD = 399, + X86_INS_PCMPGTW = 400, + X86_INS_PEXTRW = 401, + X86_INS_PHADDSW = 402, + X86_INS_PHADDW = 403, + X86_INS_PHADDD = 404, + X86_INS_PHSUBD = 405, + X86_INS_PHSUBSW = 406, + X86_INS_PHSUBW = 407, + X86_INS_PINSRW = 408, + X86_INS_PMADDUBSW = 409, + X86_INS_PMADDWD = 410, + X86_INS_PMAXSW = 411, + X86_INS_PMAXUB = 412, + X86_INS_PMINSW = 413, + X86_INS_PMINUB = 414, + X86_INS_PMOVMSKB = 415, + X86_INS_PMULHRSW = 416, + X86_INS_PMULHUW = 417, + X86_INS_PMULHW = 418, + X86_INS_PMULLW = 419, + X86_INS_PMULUDQ = 420, + X86_INS_POR = 421, + X86_INS_PSADBW = 422, + X86_INS_PSHUFB = 423, + X86_INS_PSHUFW = 424, + X86_INS_PSIGNB = 425, + X86_INS_PSIGND = 426, + X86_INS_PSIGNW = 427, + X86_INS_PSLLD = 428, + X86_INS_PSLLQ = 429, + X86_INS_PSLLW = 430, + X86_INS_PSRAD = 431, + X86_INS_PSRAW = 432, + X86_INS_PSRLD = 433, + X86_INS_PSRLQ = 434, + X86_INS_PSRLW = 435, + X86_INS_PSUBB = 436, + X86_INS_PSUBD = 437, + X86_INS_PSUBQ = 438, + X86_INS_PSUBSB = 439, + X86_INS_PSUBSW = 440, + X86_INS_PSUBUSB = 441, + X86_INS_PSUBUSW = 442, + X86_INS_PSUBW = 443, + X86_INS_PUNPCKHBW = 444, + X86_INS_PUNPCKHDQ = 445, + X86_INS_PUNPCKHWD = 446, + X86_INS_PUNPCKLBW = 447, + X86_INS_PUNPCKLDQ = 448, + X86_INS_PUNPCKLWD = 449, + X86_INS_PXOR = 450, + X86_INS_MONITOR = 451, + X86_INS_MONTMUL = 452, + X86_INS_MOV = 453, + X86_INS_MOVABS = 454, + X86_INS_MOVBE = 455, + X86_INS_MOVDDUP = 456, + X86_INS_MOVDQA = 457, + X86_INS_MOVDQU = 458, + X86_INS_MOVHLPS = 459, + X86_INS_MOVHPD = 460, + X86_INS_MOVHPS = 461, + X86_INS_MOVLHPS = 462, + X86_INS_MOVLPD = 463, + X86_INS_MOVLPS = 464, + X86_INS_MOVMSKPD = 465, + X86_INS_MOVMSKPS = 466, + X86_INS_MOVNTDQA = 467, + X86_INS_MOVNTDQ = 468, + X86_INS_MOVNTI = 469, + X86_INS_MOVNTPD = 470, + X86_INS_MOVNTPS = 471, + X86_INS_MOVNTSD = 472, + X86_INS_MOVNTSS = 473, + X86_INS_MOVSB = 474, + X86_INS_MOVSD = 475, + X86_INS_MOVSHDUP = 476, + X86_INS_MOVSLDUP = 477, + X86_INS_MOVSQ = 478, + X86_INS_MOVSS = 479, + X86_INS_MOVSW = 480, + X86_INS_MOVSX = 481, + X86_INS_MOVSXD = 482, + X86_INS_MOVUPD = 483, + X86_INS_MOVUPS = 484, + X86_INS_MOVZX = 485, + X86_INS_MPSADBW = 486, + X86_INS_MUL = 487, + X86_INS_MULPD = 488, + X86_INS_MULPS = 489, + X86_INS_MULSD = 490, + X86_INS_MULSS = 491, + X86_INS_MULX = 492, + X86_INS_FMUL = 493, + X86_INS_FIMUL = 494, + X86_INS_FMULP = 495, + X86_INS_MWAIT = 496, + X86_INS_NEG = 497, + X86_INS_NOP = 498, + X86_INS_NOT = 499, + X86_INS_OUT = 500, + X86_INS_OUTSB = 501, + X86_INS_OUTSD = 502, + X86_INS_OUTSW = 503, + X86_INS_PACKUSDW = 504, + X86_INS_PAUSE = 505, + X86_INS_PAVGUSB = 506, + X86_INS_PBLENDVB = 507, + X86_INS_PBLENDW = 508, + X86_INS_PCLMULQDQ = 509, + X86_INS_PCMPEQQ = 510, + X86_INS_PCMPESTRI = 511, + X86_INS_PCMPESTRM = 512, + X86_INS_PCMPGTQ = 513, + X86_INS_PCMPISTRI = 514, + X86_INS_PCMPISTRM = 515, + X86_INS_PCOMMIT = 516, + X86_INS_PDEP = 517, + X86_INS_PEXT = 518, + X86_INS_PEXTRB = 519, + X86_INS_PEXTRD = 520, + X86_INS_PEXTRQ = 521, + X86_INS_PF2ID = 522, + X86_INS_PF2IW = 523, + X86_INS_PFACC = 524, + X86_INS_PFADD = 525, + X86_INS_PFCMPEQ = 526, + X86_INS_PFCMPGE = 527, + X86_INS_PFCMPGT = 528, + X86_INS_PFMAX = 529, + X86_INS_PFMIN = 530, + X86_INS_PFMUL = 531, + X86_INS_PFNACC = 532, + X86_INS_PFPNACC = 533, + X86_INS_PFRCPIT1 = 534, + X86_INS_PFRCPIT2 = 535, + X86_INS_PFRCP = 536, + X86_INS_PFRSQIT1 = 537, + X86_INS_PFRSQRT = 538, + X86_INS_PFSUBR = 539, + X86_INS_PFSUB = 540, + X86_INS_PHMINPOSUW = 541, + X86_INS_PI2FD = 542, + X86_INS_PI2FW = 543, + X86_INS_PINSRB = 544, + X86_INS_PINSRD = 545, + X86_INS_PINSRQ = 546, + X86_INS_PMAXSB = 547, + X86_INS_PMAXSD = 548, + X86_INS_PMAXUD = 549, + X86_INS_PMAXUW = 550, + X86_INS_PMINSB = 551, + X86_INS_PMINSD = 552, + X86_INS_PMINUD = 553, + X86_INS_PMINUW = 554, + X86_INS_PMOVSXBD = 555, + X86_INS_PMOVSXBQ = 556, + X86_INS_PMOVSXBW = 557, + X86_INS_PMOVSXDQ = 558, + X86_INS_PMOVSXWD = 559, + X86_INS_PMOVSXWQ = 560, + X86_INS_PMOVZXBD = 561, + X86_INS_PMOVZXBQ = 562, + X86_INS_PMOVZXBW = 563, + X86_INS_PMOVZXDQ = 564, + X86_INS_PMOVZXWD = 565, + X86_INS_PMOVZXWQ = 566, + X86_INS_PMULDQ = 567, + X86_INS_PMULHRW = 568, + X86_INS_PMULLD = 569, + X86_INS_POP = 570, + X86_INS_POPAW = 571, + X86_INS_POPAL = 572, + X86_INS_POPCNT = 573, + X86_INS_POPF = 574, + X86_INS_POPFD = 575, + X86_INS_POPFQ = 576, + X86_INS_PREFETCH = 577, + X86_INS_PREFETCHNTA = 578, + X86_INS_PREFETCHT0 = 579, + X86_INS_PREFETCHT1 = 580, + X86_INS_PREFETCHT2 = 581, + X86_INS_PREFETCHW = 582, + X86_INS_PSHUFD = 583, + X86_INS_PSHUFHW = 584, + X86_INS_PSHUFLW = 585, + X86_INS_PSLLDQ = 586, + X86_INS_PSRLDQ = 587, + X86_INS_PSWAPD = 588, + X86_INS_PTEST = 589, + X86_INS_PUNPCKHQDQ = 590, + X86_INS_PUNPCKLQDQ = 591, + X86_INS_PUSH = 592, + X86_INS_PUSHAW = 593, + X86_INS_PUSHAL = 594, + X86_INS_PUSHF = 595, + X86_INS_PUSHFD = 596, + X86_INS_PUSHFQ = 597, + X86_INS_RCL = 598, + X86_INS_RCPPS = 599, + X86_INS_RCPSS = 600, + X86_INS_RCR = 601, + X86_INS_RDFSBASE = 602, + X86_INS_RDGSBASE = 603, + X86_INS_RDMSR = 604, + X86_INS_RDPMC = 605, + X86_INS_RDRAND = 606, + X86_INS_RDSEED = 607, + X86_INS_RDTSC = 608, + X86_INS_RDTSCP = 609, + X86_INS_ROL = 610, + X86_INS_ROR = 611, + X86_INS_RORX = 612, + X86_INS_ROUNDPD = 613, + X86_INS_ROUNDPS = 614, + X86_INS_ROUNDSD = 615, + X86_INS_ROUNDSS = 616, + X86_INS_RSM = 617, + X86_INS_RSQRTPS = 618, + X86_INS_RSQRTSS = 619, + X86_INS_SAHF = 620, + X86_INS_SAL = 621, + X86_INS_SALC = 622, + X86_INS_SAR = 623, + X86_INS_SARX = 624, + X86_INS_SBB = 625, + X86_INS_SCASB = 626, + X86_INS_SCASD = 627, + X86_INS_SCASQ = 628, + X86_INS_SCASW = 629, + X86_INS_SETAE = 630, + X86_INS_SETA = 631, + X86_INS_SETBE = 632, + X86_INS_SETB = 633, + X86_INS_SETE = 634, + X86_INS_SETGE = 635, + X86_INS_SETG = 636, + X86_INS_SETLE = 637, + X86_INS_SETL = 638, + X86_INS_SETNE = 639, + X86_INS_SETNO = 640, + X86_INS_SETNP = 641, + X86_INS_SETNS = 642, + X86_INS_SETO = 643, + X86_INS_SETP = 644, + X86_INS_SETS = 645, + X86_INS_SFENCE = 646, + X86_INS_SGDT = 647, + X86_INS_SHA1MSG1 = 648, + X86_INS_SHA1MSG2 = 649, + X86_INS_SHA1NEXTE = 650, + X86_INS_SHA1RNDS4 = 651, + X86_INS_SHA256MSG1 = 652, + X86_INS_SHA256MSG2 = 653, + X86_INS_SHA256RNDS2 = 654, + X86_INS_SHL = 655, + X86_INS_SHLD = 656, + X86_INS_SHLX = 657, + X86_INS_SHR = 658, + X86_INS_SHRD = 659, + X86_INS_SHRX = 660, + X86_INS_SHUFPD = 661, + X86_INS_SHUFPS = 662, + X86_INS_SIDT = 663, + X86_INS_FSIN = 664, + X86_INS_SKINIT = 665, + X86_INS_SLDT = 666, + X86_INS_SMSW = 667, + X86_INS_SQRTPD = 668, + X86_INS_SQRTPS = 669, + X86_INS_SQRTSD = 670, + X86_INS_SQRTSS = 671, + X86_INS_FSQRT = 672, + X86_INS_STAC = 673, + X86_INS_STC = 674, + X86_INS_STD = 675, + X86_INS_STGI = 676, + X86_INS_STI = 677, + X86_INS_STMXCSR = 678, + X86_INS_STOSB = 679, + X86_INS_STOSD = 680, + X86_INS_STOSQ = 681, + X86_INS_STOSW = 682, + X86_INS_STR = 683, + X86_INS_FST = 684, + X86_INS_FSTP = 685, + X86_INS_FSTPNCE = 686, + X86_INS_FXCH = 687, + X86_INS_SUBPD = 688, + X86_INS_SUBPS = 689, + X86_INS_FSUBR = 690, + X86_INS_FISUBR = 691, + X86_INS_FSUBRP = 692, + X86_INS_SUBSD = 693, + X86_INS_SUBSS = 694, + X86_INS_FSUB = 695, + X86_INS_FISUB = 696, + X86_INS_FSUBP = 697, + X86_INS_SWAPGS = 698, + X86_INS_SYSCALL = 699, + X86_INS_SYSENTER = 700, + X86_INS_SYSEXIT = 701, + X86_INS_SYSRET = 702, + X86_INS_T1MSKC = 703, + X86_INS_TEST = 704, + X86_INS_UD2 = 705, + X86_INS_FTST = 706, + X86_INS_TZCNT = 707, + X86_INS_TZMSK = 708, + X86_INS_FUCOMPI = 709, + X86_INS_FUCOMI = 710, + X86_INS_FUCOMPP = 711, + X86_INS_FUCOMP = 712, + X86_INS_FUCOM = 713, + X86_INS_UD2B = 714, + X86_INS_UNPCKHPD = 715, + X86_INS_UNPCKHPS = 716, + X86_INS_UNPCKLPD = 717, + X86_INS_UNPCKLPS = 718, + X86_INS_VADDPD = 719, + X86_INS_VADDPS = 720, + X86_INS_VADDSD = 721, + X86_INS_VADDSS = 722, + X86_INS_VADDSUBPD = 723, + X86_INS_VADDSUBPS = 724, + X86_INS_VAESDECLAST = 725, + X86_INS_VAESDEC = 726, + X86_INS_VAESENCLAST = 727, + X86_INS_VAESENC = 728, + X86_INS_VAESIMC = 729, + X86_INS_VAESKEYGENASSIST = 730, + X86_INS_VALIGND = 731, + X86_INS_VALIGNQ = 732, + X86_INS_VANDNPD = 733, + X86_INS_VANDNPS = 734, + X86_INS_VANDPD = 735, + X86_INS_VANDPS = 736, + X86_INS_VBLENDMPD = 737, + X86_INS_VBLENDMPS = 738, + X86_INS_VBLENDPD = 739, + X86_INS_VBLENDPS = 740, + X86_INS_VBLENDVPD = 741, + X86_INS_VBLENDVPS = 742, + X86_INS_VBROADCASTF128 = 743, + X86_INS_VBROADCASTI32X4 = 744, + X86_INS_VBROADCASTI64X4 = 745, + X86_INS_VBROADCASTSD = 746, + X86_INS_VBROADCASTSS = 747, + X86_INS_VCMPPD = 748, + X86_INS_VCMPPS = 749, + X86_INS_VCMPSD = 750, + X86_INS_VCMPSS = 751, + X86_INS_VCOMPRESSPD = 752, + X86_INS_VCOMPRESSPS = 753, + X86_INS_VCVTDQ2PD = 754, + X86_INS_VCVTDQ2PS = 755, + X86_INS_VCVTPD2DQX = 756, + X86_INS_VCVTPD2DQ = 757, + X86_INS_VCVTPD2PSX = 758, + X86_INS_VCVTPD2PS = 759, + X86_INS_VCVTPD2UDQ = 760, + X86_INS_VCVTPH2PS = 761, + X86_INS_VCVTPS2DQ = 762, + X86_INS_VCVTPS2PD = 763, + X86_INS_VCVTPS2PH = 764, + X86_INS_VCVTPS2UDQ = 765, + X86_INS_VCVTSD2SI = 766, + X86_INS_VCVTSD2USI = 767, + X86_INS_VCVTSS2SI = 768, + X86_INS_VCVTSS2USI = 769, + X86_INS_VCVTTPD2DQX = 770, + X86_INS_VCVTTPD2DQ = 771, + X86_INS_VCVTTPD2UDQ = 772, + X86_INS_VCVTTPS2DQ = 773, + X86_INS_VCVTTPS2UDQ = 774, + X86_INS_VCVTUDQ2PD = 775, + X86_INS_VCVTUDQ2PS = 776, + X86_INS_VDIVPD = 777, + X86_INS_VDIVPS = 778, + X86_INS_VDIVSD = 779, + X86_INS_VDIVSS = 780, + X86_INS_VDPPD = 781, + X86_INS_VDPPS = 782, + X86_INS_VERR = 783, + X86_INS_VERW = 784, + X86_INS_VEXP2PD = 785, + X86_INS_VEXP2PS = 786, + X86_INS_VEXPANDPD = 787, + X86_INS_VEXPANDPS = 788, + X86_INS_VEXTRACTF128 = 789, + X86_INS_VEXTRACTF32X4 = 790, + X86_INS_VEXTRACTF64X4 = 791, + X86_INS_VEXTRACTI128 = 792, + X86_INS_VEXTRACTI32X4 = 793, + X86_INS_VEXTRACTI64X4 = 794, + X86_INS_VEXTRACTPS = 795, + X86_INS_VFMADD132PD = 796, + X86_INS_VFMADD132PS = 797, + X86_INS_VFMADDPD = 798, + X86_INS_VFMADD213PD = 799, + X86_INS_VFMADD231PD = 800, + X86_INS_VFMADDPS = 801, + X86_INS_VFMADD213PS = 802, + X86_INS_VFMADD231PS = 803, + X86_INS_VFMADDSD = 804, + X86_INS_VFMADD213SD = 805, + X86_INS_VFMADD132SD = 806, + X86_INS_VFMADD231SD = 807, + X86_INS_VFMADDSS = 808, + X86_INS_VFMADD213SS = 809, + X86_INS_VFMADD132SS = 810, + X86_INS_VFMADD231SS = 811, + X86_INS_VFMADDSUB132PD = 812, + X86_INS_VFMADDSUB132PS = 813, + X86_INS_VFMADDSUBPD = 814, + X86_INS_VFMADDSUB213PD = 815, + X86_INS_VFMADDSUB231PD = 816, + X86_INS_VFMADDSUBPS = 817, + X86_INS_VFMADDSUB213PS = 818, + X86_INS_VFMADDSUB231PS = 819, + X86_INS_VFMSUB132PD = 820, + X86_INS_VFMSUB132PS = 821, + X86_INS_VFMSUBADD132PD = 822, + X86_INS_VFMSUBADD132PS = 823, + X86_INS_VFMSUBADDPD = 824, + X86_INS_VFMSUBADD213PD = 825, + X86_INS_VFMSUBADD231PD = 826, + X86_INS_VFMSUBADDPS = 827, + X86_INS_VFMSUBADD213PS = 828, + X86_INS_VFMSUBADD231PS = 829, + X86_INS_VFMSUBPD = 830, + X86_INS_VFMSUB213PD = 831, + X86_INS_VFMSUB231PD = 832, + X86_INS_VFMSUBPS = 833, + X86_INS_VFMSUB213PS = 834, + X86_INS_VFMSUB231PS = 835, + X86_INS_VFMSUBSD = 836, + X86_INS_VFMSUB213SD = 837, + X86_INS_VFMSUB132SD = 838, + X86_INS_VFMSUB231SD = 839, + X86_INS_VFMSUBSS = 840, + X86_INS_VFMSUB213SS = 841, + X86_INS_VFMSUB132SS = 842, + X86_INS_VFMSUB231SS = 843, + X86_INS_VFNMADD132PD = 844, + X86_INS_VFNMADD132PS = 845, + X86_INS_VFNMADDPD = 846, + X86_INS_VFNMADD213PD = 847, + X86_INS_VFNMADD231PD = 848, + X86_INS_VFNMADDPS = 849, + X86_INS_VFNMADD213PS = 850, + X86_INS_VFNMADD231PS = 851, + X86_INS_VFNMADDSD = 852, + X86_INS_VFNMADD213SD = 853, + X86_INS_VFNMADD132SD = 854, + X86_INS_VFNMADD231SD = 855, + X86_INS_VFNMADDSS = 856, + X86_INS_VFNMADD213SS = 857, + X86_INS_VFNMADD132SS = 858, + X86_INS_VFNMADD231SS = 859, + X86_INS_VFNMSUB132PD = 860, + X86_INS_VFNMSUB132PS = 861, + X86_INS_VFNMSUBPD = 862, + X86_INS_VFNMSUB213PD = 863, + X86_INS_VFNMSUB231PD = 864, + X86_INS_VFNMSUBPS = 865, + X86_INS_VFNMSUB213PS = 866, + X86_INS_VFNMSUB231PS = 867, + X86_INS_VFNMSUBSD = 868, + X86_INS_VFNMSUB213SD = 869, + X86_INS_VFNMSUB132SD = 870, + X86_INS_VFNMSUB231SD = 871, + X86_INS_VFNMSUBSS = 872, + X86_INS_VFNMSUB213SS = 873, + X86_INS_VFNMSUB132SS = 874, + X86_INS_VFNMSUB231SS = 875, + X86_INS_VFRCZPD = 876, + X86_INS_VFRCZPS = 877, + X86_INS_VFRCZSD = 878, + X86_INS_VFRCZSS = 879, + X86_INS_VORPD = 880, + X86_INS_VORPS = 881, + X86_INS_VXORPD = 882, + X86_INS_VXORPS = 883, + X86_INS_VGATHERDPD = 884, + X86_INS_VGATHERDPS = 885, + X86_INS_VGATHERPF0DPD = 886, + X86_INS_VGATHERPF0DPS = 887, + X86_INS_VGATHERPF0QPD = 888, + X86_INS_VGATHERPF0QPS = 889, + X86_INS_VGATHERPF1DPD = 890, + X86_INS_VGATHERPF1DPS = 891, + X86_INS_VGATHERPF1QPD = 892, + X86_INS_VGATHERPF1QPS = 893, + X86_INS_VGATHERQPD = 894, + X86_INS_VGATHERQPS = 895, + X86_INS_VHADDPD = 896, + X86_INS_VHADDPS = 897, + X86_INS_VHSUBPD = 898, + X86_INS_VHSUBPS = 899, + X86_INS_VINSERTF128 = 900, + X86_INS_VINSERTF32X4 = 901, + X86_INS_VINSERTF32X8 = 902, + X86_INS_VINSERTF64X2 = 903, + X86_INS_VINSERTF64X4 = 904, + X86_INS_VINSERTI128 = 905, + X86_INS_VINSERTI32X4 = 906, + X86_INS_VINSERTI32X8 = 907, + X86_INS_VINSERTI64X2 = 908, + X86_INS_VINSERTI64X4 = 909, + X86_INS_VINSERTPS = 910, + X86_INS_VLDDQU = 911, + X86_INS_VLDMXCSR = 912, + X86_INS_VMASKMOVDQU = 913, + X86_INS_VMASKMOVPD = 914, + X86_INS_VMASKMOVPS = 915, + X86_INS_VMAXPD = 916, + X86_INS_VMAXPS = 917, + X86_INS_VMAXSD = 918, + X86_INS_VMAXSS = 919, + X86_INS_VMCALL = 920, + X86_INS_VMCLEAR = 921, + X86_INS_VMFUNC = 922, + X86_INS_VMINPD = 923, + X86_INS_VMINPS = 924, + X86_INS_VMINSD = 925, + X86_INS_VMINSS = 926, + X86_INS_VMLAUNCH = 927, + X86_INS_VMLOAD = 928, + X86_INS_VMMCALL = 929, + X86_INS_VMOVQ = 930, + X86_INS_VMOVDDUP = 931, + X86_INS_VMOVD = 932, + X86_INS_VMOVDQA32 = 933, + X86_INS_VMOVDQA64 = 934, + X86_INS_VMOVDQA = 935, + X86_INS_VMOVDQU16 = 936, + X86_INS_VMOVDQU32 = 937, + X86_INS_VMOVDQU64 = 938, + X86_INS_VMOVDQU8 = 939, + X86_INS_VMOVDQU = 940, + X86_INS_VMOVHLPS = 941, + X86_INS_VMOVHPD = 942, + X86_INS_VMOVHPS = 943, + X86_INS_VMOVLHPS = 944, + X86_INS_VMOVLPD = 945, + X86_INS_VMOVLPS = 946, + X86_INS_VMOVMSKPD = 947, + X86_INS_VMOVMSKPS = 948, + X86_INS_VMOVNTDQA = 949, + X86_INS_VMOVNTDQ = 950, + X86_INS_VMOVNTPD = 951, + X86_INS_VMOVNTPS = 952, + X86_INS_VMOVSD = 953, + X86_INS_VMOVSHDUP = 954, + X86_INS_VMOVSLDUP = 955, + X86_INS_VMOVSS = 956, + X86_INS_VMOVUPD = 957, + X86_INS_VMOVUPS = 958, + X86_INS_VMPSADBW = 959, + X86_INS_VMPTRLD = 960, + X86_INS_VMPTRST = 961, + X86_INS_VMREAD = 962, + X86_INS_VMRESUME = 963, + X86_INS_VMRUN = 964, + X86_INS_VMSAVE = 965, + X86_INS_VMULPD = 966, + X86_INS_VMULPS = 967, + X86_INS_VMULSD = 968, + X86_INS_VMULSS = 969, + X86_INS_VMWRITE = 970, + X86_INS_VMXOFF = 971, + X86_INS_VMXON = 972, + X86_INS_VPABSB = 973, + X86_INS_VPABSD = 974, + X86_INS_VPABSQ = 975, + X86_INS_VPABSW = 976, + X86_INS_VPACKSSDW = 977, + X86_INS_VPACKSSWB = 978, + X86_INS_VPACKUSDW = 979, + X86_INS_VPACKUSWB = 980, + X86_INS_VPADDB = 981, + X86_INS_VPADDD = 982, + X86_INS_VPADDQ = 983, + X86_INS_VPADDSB = 984, + X86_INS_VPADDSW = 985, + X86_INS_VPADDUSB = 986, + X86_INS_VPADDUSW = 987, + X86_INS_VPADDW = 988, + X86_INS_VPALIGNR = 989, + X86_INS_VPANDD = 990, + X86_INS_VPANDND = 991, + X86_INS_VPANDNQ = 992, + X86_INS_VPANDN = 993, + X86_INS_VPANDQ = 994, + X86_INS_VPAND = 995, + X86_INS_VPAVGB = 996, + X86_INS_VPAVGW = 997, + X86_INS_VPBLENDD = 998, + X86_INS_VPBLENDMB = 999, + X86_INS_VPBLENDMD = 1000, + X86_INS_VPBLENDMQ = 1001, + X86_INS_VPBLENDMW = 1002, + X86_INS_VPBLENDVB = 1003, + X86_INS_VPBLENDW = 1004, + X86_INS_VPBROADCASTB = 1005, + X86_INS_VPBROADCASTD = 1006, + X86_INS_VPBROADCASTMB2Q = 1007, + X86_INS_VPBROADCASTMW2D = 1008, + X86_INS_VPBROADCASTQ = 1009, + X86_INS_VPBROADCASTW = 1010, + X86_INS_VPCLMULQDQ = 1011, + X86_INS_VPCMOV = 1012, + X86_INS_VPCMPB = 1013, + X86_INS_VPCMPD = 1014, + X86_INS_VPCMPEQB = 1015, + X86_INS_VPCMPEQD = 1016, + X86_INS_VPCMPEQQ = 1017, + X86_INS_VPCMPEQW = 1018, + X86_INS_VPCMPESTRI = 1019, + X86_INS_VPCMPESTRM = 1020, + X86_INS_VPCMPGTB = 1021, + X86_INS_VPCMPGTD = 1022, + X86_INS_VPCMPGTQ = 1023, + X86_INS_VPCMPGTW = 1024, + X86_INS_VPCMPISTRI = 1025, + X86_INS_VPCMPISTRM = 1026, + X86_INS_VPCMPQ = 1027, + X86_INS_VPCMPUB = 1028, + X86_INS_VPCMPUD = 1029, + X86_INS_VPCMPUQ = 1030, + X86_INS_VPCMPUW = 1031, + X86_INS_VPCMPW = 1032, + X86_INS_VPCOMB = 1033, + X86_INS_VPCOMD = 1034, + X86_INS_VPCOMPRESSD = 1035, + X86_INS_VPCOMPRESSQ = 1036, + X86_INS_VPCOMQ = 1037, + X86_INS_VPCOMUB = 1038, + X86_INS_VPCOMUD = 1039, + X86_INS_VPCOMUQ = 1040, + X86_INS_VPCOMUW = 1041, + X86_INS_VPCOMW = 1042, + X86_INS_VPCONFLICTD = 1043, + X86_INS_VPCONFLICTQ = 1044, + X86_INS_VPERM2F128 = 1045, + X86_INS_VPERM2I128 = 1046, + X86_INS_VPERMD = 1047, + X86_INS_VPERMI2D = 1048, + X86_INS_VPERMI2PD = 1049, + X86_INS_VPERMI2PS = 1050, + X86_INS_VPERMI2Q = 1051, + X86_INS_VPERMIL2PD = 1052, + X86_INS_VPERMIL2PS = 1053, + X86_INS_VPERMILPD = 1054, + X86_INS_VPERMILPS = 1055, + X86_INS_VPERMPD = 1056, + X86_INS_VPERMPS = 1057, + X86_INS_VPERMQ = 1058, + X86_INS_VPERMT2D = 1059, + X86_INS_VPERMT2PD = 1060, + X86_INS_VPERMT2PS = 1061, + X86_INS_VPERMT2Q = 1062, + X86_INS_VPEXPANDD = 1063, + X86_INS_VPEXPANDQ = 1064, + X86_INS_VPEXTRB = 1065, + X86_INS_VPEXTRD = 1066, + X86_INS_VPEXTRQ = 1067, + X86_INS_VPEXTRW = 1068, + X86_INS_VPGATHERDD = 1069, + X86_INS_VPGATHERDQ = 1070, + X86_INS_VPGATHERQD = 1071, + X86_INS_VPGATHERQQ = 1072, + X86_INS_VPHADDBD = 1073, + X86_INS_VPHADDBQ = 1074, + X86_INS_VPHADDBW = 1075, + X86_INS_VPHADDDQ = 1076, + X86_INS_VPHADDD = 1077, + X86_INS_VPHADDSW = 1078, + X86_INS_VPHADDUBD = 1079, + X86_INS_VPHADDUBQ = 1080, + X86_INS_VPHADDUBW = 1081, + X86_INS_VPHADDUDQ = 1082, + X86_INS_VPHADDUWD = 1083, + X86_INS_VPHADDUWQ = 1084, + X86_INS_VPHADDWD = 1085, + X86_INS_VPHADDWQ = 1086, + X86_INS_VPHADDW = 1087, + X86_INS_VPHMINPOSUW = 1088, + X86_INS_VPHSUBBW = 1089, + X86_INS_VPHSUBDQ = 1090, + X86_INS_VPHSUBD = 1091, + X86_INS_VPHSUBSW = 1092, + X86_INS_VPHSUBWD = 1093, + X86_INS_VPHSUBW = 1094, + X86_INS_VPINSRB = 1095, + X86_INS_VPINSRD = 1096, + X86_INS_VPINSRQ = 1097, + X86_INS_VPINSRW = 1098, + X86_INS_VPLZCNTD = 1099, + X86_INS_VPLZCNTQ = 1100, + X86_INS_VPMACSDD = 1101, + X86_INS_VPMACSDQH = 1102, + X86_INS_VPMACSDQL = 1103, + X86_INS_VPMACSSDD = 1104, + X86_INS_VPMACSSDQH = 1105, + X86_INS_VPMACSSDQL = 1106, + X86_INS_VPMACSSWD = 1107, + X86_INS_VPMACSSWW = 1108, + X86_INS_VPMACSWD = 1109, + X86_INS_VPMACSWW = 1110, + X86_INS_VPMADCSSWD = 1111, + X86_INS_VPMADCSWD = 1112, + X86_INS_VPMADDUBSW = 1113, + X86_INS_VPMADDWD = 1114, + X86_INS_VPMASKMOVD = 1115, + X86_INS_VPMASKMOVQ = 1116, + X86_INS_VPMAXSB = 1117, + X86_INS_VPMAXSD = 1118, + X86_INS_VPMAXSQ = 1119, + X86_INS_VPMAXSW = 1120, + X86_INS_VPMAXUB = 1121, + X86_INS_VPMAXUD = 1122, + X86_INS_VPMAXUQ = 1123, + X86_INS_VPMAXUW = 1124, + X86_INS_VPMINSB = 1125, + X86_INS_VPMINSD = 1126, + X86_INS_VPMINSQ = 1127, + X86_INS_VPMINSW = 1128, + X86_INS_VPMINUB = 1129, + X86_INS_VPMINUD = 1130, + X86_INS_VPMINUQ = 1131, + X86_INS_VPMINUW = 1132, + X86_INS_VPMOVDB = 1133, + X86_INS_VPMOVDW = 1134, + X86_INS_VPMOVM2B = 1135, + X86_INS_VPMOVM2D = 1136, + X86_INS_VPMOVM2Q = 1137, + X86_INS_VPMOVM2W = 1138, + X86_INS_VPMOVMSKB = 1139, + X86_INS_VPMOVQB = 1140, + X86_INS_VPMOVQD = 1141, + X86_INS_VPMOVQW = 1142, + X86_INS_VPMOVSDB = 1143, + X86_INS_VPMOVSDW = 1144, + X86_INS_VPMOVSQB = 1145, + X86_INS_VPMOVSQD = 1146, + X86_INS_VPMOVSQW = 1147, + X86_INS_VPMOVSXBD = 1148, + X86_INS_VPMOVSXBQ = 1149, + X86_INS_VPMOVSXBW = 1150, + X86_INS_VPMOVSXDQ = 1151, + X86_INS_VPMOVSXWD = 1152, + X86_INS_VPMOVSXWQ = 1153, + X86_INS_VPMOVUSDB = 1154, + X86_INS_VPMOVUSDW = 1155, + X86_INS_VPMOVUSQB = 1156, + X86_INS_VPMOVUSQD = 1157, + X86_INS_VPMOVUSQW = 1158, + X86_INS_VPMOVZXBD = 1159, + X86_INS_VPMOVZXBQ = 1160, + X86_INS_VPMOVZXBW = 1161, + X86_INS_VPMOVZXDQ = 1162, + X86_INS_VPMOVZXWD = 1163, + X86_INS_VPMOVZXWQ = 1164, + X86_INS_VPMULDQ = 1165, + X86_INS_VPMULHRSW = 1166, + X86_INS_VPMULHUW = 1167, + X86_INS_VPMULHW = 1168, + X86_INS_VPMULLD = 1169, + X86_INS_VPMULLQ = 1170, + X86_INS_VPMULLW = 1171, + X86_INS_VPMULUDQ = 1172, + X86_INS_VPORD = 1173, + X86_INS_VPORQ = 1174, + X86_INS_VPOR = 1175, + X86_INS_VPPERM = 1176, + X86_INS_VPROTB = 1177, + X86_INS_VPROTD = 1178, + X86_INS_VPROTQ = 1179, + X86_INS_VPROTW = 1180, + X86_INS_VPSADBW = 1181, + X86_INS_VPSCATTERDD = 1182, + X86_INS_VPSCATTERDQ = 1183, + X86_INS_VPSCATTERQD = 1184, + X86_INS_VPSCATTERQQ = 1185, + X86_INS_VPSHAB = 1186, + X86_INS_VPSHAD = 1187, + X86_INS_VPSHAQ = 1188, + X86_INS_VPSHAW = 1189, + X86_INS_VPSHLB = 1190, + X86_INS_VPSHLD = 1191, + X86_INS_VPSHLQ = 1192, + X86_INS_VPSHLW = 1193, + X86_INS_VPSHUFB = 1194, + X86_INS_VPSHUFD = 1195, + X86_INS_VPSHUFHW = 1196, + X86_INS_VPSHUFLW = 1197, + X86_INS_VPSIGNB = 1198, + X86_INS_VPSIGND = 1199, + X86_INS_VPSIGNW = 1200, + X86_INS_VPSLLDQ = 1201, + X86_INS_VPSLLD = 1202, + X86_INS_VPSLLQ = 1203, + X86_INS_VPSLLVD = 1204, + X86_INS_VPSLLVQ = 1205, + X86_INS_VPSLLW = 1206, + X86_INS_VPSRAD = 1207, + X86_INS_VPSRAQ = 1208, + X86_INS_VPSRAVD = 1209, + X86_INS_VPSRAVQ = 1210, + X86_INS_VPSRAW = 1211, + X86_INS_VPSRLDQ = 1212, + X86_INS_VPSRLD = 1213, + X86_INS_VPSRLQ = 1214, + X86_INS_VPSRLVD = 1215, + X86_INS_VPSRLVQ = 1216, + X86_INS_VPSRLW = 1217, + X86_INS_VPSUBB = 1218, + X86_INS_VPSUBD = 1219, + X86_INS_VPSUBQ = 1220, + X86_INS_VPSUBSB = 1221, + X86_INS_VPSUBSW = 1222, + X86_INS_VPSUBUSB = 1223, + X86_INS_VPSUBUSW = 1224, + X86_INS_VPSUBW = 1225, + X86_INS_VPTESTMD = 1226, + X86_INS_VPTESTMQ = 1227, + X86_INS_VPTESTNMD = 1228, + X86_INS_VPTESTNMQ = 1229, + X86_INS_VPTEST = 1230, + X86_INS_VPUNPCKHBW = 1231, + X86_INS_VPUNPCKHDQ = 1232, + X86_INS_VPUNPCKHQDQ = 1233, + X86_INS_VPUNPCKHWD = 1234, + X86_INS_VPUNPCKLBW = 1235, + X86_INS_VPUNPCKLDQ = 1236, + X86_INS_VPUNPCKLQDQ = 1237, + X86_INS_VPUNPCKLWD = 1238, + X86_INS_VPXORD = 1239, + X86_INS_VPXORQ = 1240, + X86_INS_VPXOR = 1241, + X86_INS_VRCP14PD = 1242, + X86_INS_VRCP14PS = 1243, + X86_INS_VRCP14SD = 1244, + X86_INS_VRCP14SS = 1245, + X86_INS_VRCP28PD = 1246, + X86_INS_VRCP28PS = 1247, + X86_INS_VRCP28SD = 1248, + X86_INS_VRCP28SS = 1249, + X86_INS_VRCPPS = 1250, + X86_INS_VRCPSS = 1251, + X86_INS_VRNDSCALEPD = 1252, + X86_INS_VRNDSCALEPS = 1253, + X86_INS_VRNDSCALESD = 1254, + X86_INS_VRNDSCALESS = 1255, + X86_INS_VROUNDPD = 1256, + X86_INS_VROUNDPS = 1257, + X86_INS_VROUNDSD = 1258, + X86_INS_VROUNDSS = 1259, + X86_INS_VRSQRT14PD = 1260, + X86_INS_VRSQRT14PS = 1261, + X86_INS_VRSQRT14SD = 1262, + X86_INS_VRSQRT14SS = 1263, + X86_INS_VRSQRT28PD = 1264, + X86_INS_VRSQRT28PS = 1265, + X86_INS_VRSQRT28SD = 1266, + X86_INS_VRSQRT28SS = 1267, + X86_INS_VRSQRTPS = 1268, + X86_INS_VRSQRTSS = 1269, + X86_INS_VSCATTERDPD = 1270, + X86_INS_VSCATTERDPS = 1271, + X86_INS_VSCATTERPF0DPD = 1272, + X86_INS_VSCATTERPF0DPS = 1273, + X86_INS_VSCATTERPF0QPD = 1274, + X86_INS_VSCATTERPF0QPS = 1275, + X86_INS_VSCATTERPF1DPD = 1276, + X86_INS_VSCATTERPF1DPS = 1277, + X86_INS_VSCATTERPF1QPD = 1278, + X86_INS_VSCATTERPF1QPS = 1279, + X86_INS_VSCATTERQPD = 1280, + X86_INS_VSCATTERQPS = 1281, + X86_INS_VSHUFPD = 1282, + X86_INS_VSHUFPS = 1283, + X86_INS_VSQRTPD = 1284, + X86_INS_VSQRTPS = 1285, + X86_INS_VSQRTSD = 1286, + X86_INS_VSQRTSS = 1287, + X86_INS_VSTMXCSR = 1288, + X86_INS_VSUBPD = 1289, + X86_INS_VSUBPS = 1290, + X86_INS_VSUBSD = 1291, + X86_INS_VSUBSS = 1292, + X86_INS_VTESTPD = 1293, + X86_INS_VTESTPS = 1294, + X86_INS_VUNPCKHPD = 1295, + X86_INS_VUNPCKHPS = 1296, + X86_INS_VUNPCKLPD = 1297, + X86_INS_VUNPCKLPS = 1298, + X86_INS_VZEROALL = 1299, + X86_INS_VZEROUPPER = 1300, + X86_INS_WAIT = 1301, + X86_INS_WBINVD = 1302, + X86_INS_WRFSBASE = 1303, + X86_INS_WRGSBASE = 1304, + X86_INS_WRMSR = 1305, + X86_INS_XABORT = 1306, + X86_INS_XACQUIRE = 1307, + X86_INS_XBEGIN = 1308, + X86_INS_XCHG = 1309, + X86_INS_XCRYPTCBC = 1310, + X86_INS_XCRYPTCFB = 1311, + X86_INS_XCRYPTCTR = 1312, + X86_INS_XCRYPTECB = 1313, + X86_INS_XCRYPTOFB = 1314, + X86_INS_XEND = 1315, + X86_INS_XGETBV = 1316, + X86_INS_XLATB = 1317, + X86_INS_XRELEASE = 1318, + X86_INS_XRSTOR = 1319, + X86_INS_XRSTOR64 = 1320, + X86_INS_XRSTORS = 1321, + X86_INS_XRSTORS64 = 1322, + X86_INS_XSAVE = 1323, + X86_INS_XSAVE64 = 1324, + X86_INS_XSAVEC = 1325, + X86_INS_XSAVEC64 = 1326, + X86_INS_XSAVEOPT = 1327, + X86_INS_XSAVEOPT64 = 1328, + X86_INS_XSAVES = 1329, + X86_INS_XSAVES64 = 1330, + X86_INS_XSETBV = 1331, + X86_INS_XSHA1 = 1332, + X86_INS_XSHA256 = 1333, + X86_INS_XSTORE = 1334, + X86_INS_XTEST = 1335, + X86_INS_FDISI8087_NOP = 1336, + X86_INS_FENI8087_NOP = 1337, + X86_INS_ENDING = 1338, + +}; From 48ce4164b3cf5a5311b7bef97c6967eef895b424 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matheus=20C=2E=20Fran=C3=A7a?= Date: Thu, 23 Mar 2023 16:15:33 -0300 Subject: [PATCH 2/3] new binding --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index c817cfda..87d8a159 100644 --- a/README.md +++ b/README.md @@ -15,7 +15,7 @@ Unicorn offers some unparalleled features: - Multi-architecture: ARM, ARM64 (ARMv8), M68K, MIPS, PowerPC, RISCV, SPARC, S390X, TriCore and X86 (16, 32, 64-bit) - Clean/simple/lightweight/intuitive architecture-neutral API -- Implemented in pure C language, with bindings for Crystal, Clojure, Visual Basic, Perl, Rust, Ruby, Python, Java, .NET, Go, Delphi/Free Pascal, Haskell, Pharo, and Lua. +- Implemented in pure C language, with bindings for Crystal, Clojure, Visual Basic, Perl, Rust, Ruby, Python, Java, .NET, Go, Delphi/Free Pascal, Haskell, Pharo, Lua and Zig. - Native support for Windows & *nix (with Mac OSX, Linux, Android, *BSD & Solaris confirmed) - High performance via Just-In-Time compilation - Support for fine-grained instrumentation at various levels From 81a85368419febf01e47bc7b7f66dc391ed28555 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matheus=20C=2E=20Fran=C3=A7a?= Date: Thu, 23 Mar 2023 16:16:18 -0300 Subject: [PATCH 3/3] Update Cargo.toml exclude new binding on rust build --- Cargo.toml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index 3d6d388d..86ff6dc6 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -22,6 +22,7 @@ exclude = [ "/bindings/python", "/bindings/ruby", "/bindings/vb6", + "/bindings/zig", "/samples", "/tests", ] @@ -40,4 +41,4 @@ pkg-config = { version = "0.3" } [features] default = [] -dynamic_linkage = [] \ No newline at end of file +dynamic_linkage = []