From 2181f187ba280ea95a8c2f9cd96a319d145eaa7c Mon Sep 17 00:00:00 2001
From: elicn <elichn@gmail.com>
Date: Sat, 28 Sep 2024 22:11:01 +0300
Subject: [PATCH] Add read and write cases for i386 CR8

---
 qemu/target/i386/cpu.h     | 2 +-
 qemu/target/i386/unicorn.c | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/qemu/target/i386/cpu.h b/qemu/target/i386/cpu.h
index b16ebd29..4ddb7a51 100644
--- a/qemu/target/i386/cpu.h
+++ b/qemu/target/i386/cpu.h
@@ -1397,7 +1397,7 @@ typedef struct CPUX86State {
     SegmentCache gdt; /* only base and limit are used */
     SegmentCache idt; /* only base and limit are used */
 
-    target_ulong cr[5]; /* NOTE: cr1 is unused */
+    target_ulong cr[9]; /* NOTE: cr1, cr5-cr7 are not used */
     int32_t a20_mask;
 
     BNDReg bnd_regs[4];
diff --git a/qemu/target/i386/unicorn.c b/qemu/target/i386/unicorn.c
index ceddb55d..0172999b 100644
--- a/qemu/target/i386/unicorn.c
+++ b/qemu/target/i386/unicorn.c
@@ -594,6 +594,7 @@ uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
         case UC_X86_REG_CR2:
         case UC_X86_REG_CR3:
         case UC_X86_REG_CR4:
+        case UC_X86_REG_CR8:
             CHECK_REG_TYPE(int64_t);
             *(int64_t *)value = env->cr[regid - UC_X86_REG_CR0];
             break;
@@ -1402,6 +1403,9 @@ uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
         case UC_X86_REG_CR4:
             CHECK_REG_TYPE(uint64_t);
             cpu_x86_update_cr4(env, *(uint32_t *)value);
+            goto write_cr64;
+        case UC_X86_REG_CR8:
+            CHECK_REG_TYPE(uint64_t);
         write_cr64:
             env->cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value;
             break;