From 187b470245fcce50bda61fc1abbd5acf9725169b Mon Sep 17 00:00:00 2001 From: Ryan Hileman Date: Mon, 1 May 2017 23:51:19 -0700 Subject: [PATCH] add arm64 CPACR_EL1 register support (#814) --- bindings/dotnet/UnicornManaged/Const/Arm64.fs | 3 ++- bindings/go/unicorn/arm64_const.go | 3 ++- bindings/java/unicorn/Arm64Const.java | 3 ++- bindings/python/unicorn/arm64_const.py | 3 ++- bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb | 3 ++- include/unicorn/arm64.h | 2 ++ qemu/target-arm/unicorn_aarch64.c | 6 ++++++ 7 files changed, 18 insertions(+), 5 deletions(-) diff --git a/bindings/dotnet/UnicornManaged/Const/Arm64.fs b/bindings/dotnet/UnicornManaged/Const/Arm64.fs index bb1a2140..4801732f 100644 --- a/bindings/dotnet/UnicornManaged/Const/Arm64.fs +++ b/bindings/dotnet/UnicornManaged/Const/Arm64.fs @@ -272,7 +272,8 @@ module Arm64 = // pseudo registers let UC_ARM64_REG_PC = 260 - let UC_ARM64_REG_ENDING = 261 + let UC_ARM64_REG_CPACR_EL1 = 261 + let UC_ARM64_REG_ENDING = 262 // alias registers let UC_ARM64_REG_IP1 = 215 diff --git a/bindings/go/unicorn/arm64_const.go b/bindings/go/unicorn/arm64_const.go index 97c6a656..47a90c8c 100644 --- a/bindings/go/unicorn/arm64_const.go +++ b/bindings/go/unicorn/arm64_const.go @@ -267,7 +267,8 @@ const ( // pseudo registers ARM64_REG_PC = 260 - ARM64_REG_ENDING = 261 + ARM64_REG_CPACR_EL1 = 261 + ARM64_REG_ENDING = 262 // alias registers ARM64_REG_IP1 = 215 diff --git a/bindings/java/unicorn/Arm64Const.java b/bindings/java/unicorn/Arm64Const.java index 6104a277..9b79fbfb 100644 --- a/bindings/java/unicorn/Arm64Const.java +++ b/bindings/java/unicorn/Arm64Const.java @@ -269,7 +269,8 @@ public interface Arm64Const { // pseudo registers public static final int UC_ARM64_REG_PC = 260; - public static final int UC_ARM64_REG_ENDING = 261; + public static final int UC_ARM64_REG_CPACR_EL1 = 261; + public static final int UC_ARM64_REG_ENDING = 262; // alias registers public static final int UC_ARM64_REG_IP1 = 215; diff --git a/bindings/python/unicorn/arm64_const.py b/bindings/python/unicorn/arm64_const.py index 86d6881a..30001560 100644 --- a/bindings/python/unicorn/arm64_const.py +++ b/bindings/python/unicorn/arm64_const.py @@ -265,7 +265,8 @@ UC_ARM64_REG_V31 = 259 # pseudo registers UC_ARM64_REG_PC = 260 -UC_ARM64_REG_ENDING = 261 +UC_ARM64_REG_CPACR_EL1 = 261 +UC_ARM64_REG_ENDING = 262 # alias registers UC_ARM64_REG_IP1 = 215 diff --git a/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb index 7767d96b..e1abdf76 100644 --- a/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb +++ b/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb @@ -267,7 +267,8 @@ module Unicorn # pseudo registers UC_ARM64_REG_PC = 260 - UC_ARM64_REG_ENDING = 261 + UC_ARM64_REG_CPACR_EL1 = 261 + UC_ARM64_REG_ENDING = 262 # alias registers UC_ARM64_REG_IP1 = 215 diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h index 12619abc..17eb7b78 100644 --- a/include/unicorn/arm64.h +++ b/include/unicorn/arm64.h @@ -280,6 +280,8 @@ typedef enum uc_arm64_reg { //> pseudo registers UC_ARM64_REG_PC, // program counter register + UC_ARM64_REG_CPACR_EL1, + UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers //> alias registers diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c index 93d82ce1..3de2dbab 100644 --- a/qemu/target-arm/unicorn_aarch64.c +++ b/qemu/target-arm/unicorn_aarch64.c @@ -76,6 +76,9 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co } else { switch(regid) { default: break; + case UC_ARM64_REG_CPACR_EL1: + *(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.c1_coproc; + break; case UC_ARM64_REG_X29: *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[29]; break; @@ -129,6 +132,9 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, } else { switch(regid) { default: break; + case UC_ARM64_REG_CPACR_EL1: + ARM_CPU(uc, mycpu)->env.cp15.c1_coproc = *(uint32_t *)value; + break; case UC_ARM64_REG_X29: ARM_CPU(uc, mycpu)->env.xregs[29] = *(uint64_t *)value; break;