add regress for #157

2015-09-27 01:08:46 -07:00 · 2015-09-27 01:08:46 -07:00 · 13be3435c9
parent 53ce8f217d
commit 13be3435c9
1 changed files with 16 additions and 0 deletions
--- a/tests/regress/mips_syscall_pc.py
+++ b/tests/regress/mips_syscall_pc.py
@ -0,0 +1,16 @@
+from unicorn import *
+from unicorn.mips_const import *
+
+def intr_hook(uc, intno, data):
+    print 'interrupt=%d, v0=%d, pc=0x%08x' % (intno, uc.reg_read(UC_MIPS_REG_V0), uc.reg_read(UC_MIPS_REG_PC))
+
+addr = 0x40000
+code = '0c000000'.decode('hex') # syscall
+
+uc = Uc(UC_ARCH_MIPS, UC_MODE_MIPS32 + UC_MODE_LITTLE_ENDIAN)
+uc.mem_map(addr, 0x1000)
+uc.mem_write(addr, code)
+uc.reg_write(UC_MIPS_REG_V0, 100)
+uc.hook_add(UC_HOOK_INTR, intr_hook)
+
+uc.emu_start(addr, len(code))