From 59b09a71bfc6fd8b95357944f6be9aa54f424421 Mon Sep 17 00:00:00 2001 From: mothran Date: Thu, 27 Aug 2015 21:54:23 -0700 Subject: [PATCH 01/10] first shot at getting FPIP working, need to remove all FP control instructions from being updated --- qemu/target-i386/fpu_helper.c | 2 +- qemu/target-i386/translate.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/qemu/target-i386/fpu_helper.c b/qemu/target-i386/fpu_helper.c index 1d4eee39..fa20b7a1 100644 --- a/qemu/target-i386/fpu_helper.c +++ b/qemu/target-i386/fpu_helper.c @@ -991,7 +991,7 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) cpu_stl_data(env, ptr, env->fpuc); cpu_stl_data(env, ptr + 4, fpus); cpu_stl_data(env, ptr + 8, fptag); - cpu_stl_data(env, ptr + 12, 0); /* fpip */ + cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */ cpu_stl_data(env, ptr + 16, 0); /* fpcs */ cpu_stl_data(env, ptr + 20, 0); /* fpoo */ cpu_stl_data(env, ptr + 24, 0); /* fpos */ diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c index 7ce37ef8..d48ed3c8 100644 --- a/qemu/target-i386/translate.c +++ b/qemu/target-i386/translate.c @@ -248,6 +248,11 @@ static void gen_update_cc_op(DisasContext *s) } } +static void fpu_update_ip(CPUX86State *env) +{ + env->fpip = env->eip; +} + #ifdef TARGET_X86_64 #define NB_OP_SIZES 4 @@ -6065,6 +6070,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); break; } + fpu_update_ip(env); modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; rm = modrm & 7; From 933ef379b4b11f10b430536cee2db4d5665fbb6b Mon Sep 17 00:00:00 2001 From: mothran Date: Fri, 28 Aug 2015 03:19:10 -0700 Subject: [PATCH 02/10] restricted fpip updates to only non-control instructions --- qemu/target-i386/translate.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c index d48ed3c8..5b4ccb25 100644 --- a/qemu/target-i386/translate.c +++ b/qemu/target-i386/translate.c @@ -6070,7 +6070,6 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); break; } - fpu_update_ip(env); modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; rm = modrm & 7; @@ -6116,6 +6115,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* fcomp needs pop */ gen_helper_fpop(tcg_ctx, cpu_env); } + fpu_update_ip(env); } break; case 0x08: /* flds */ @@ -6200,6 +6200,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_fpop(tcg_ctx, cpu_env); break; } + fpu_update_ip(env); break; case 0x0c: /* fldenv mem */ gen_update_cc_op(s); @@ -6225,12 +6226,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fldt_ST0(tcg_ctx, cpu_env, cpu_A0); + fpu_update_ip(env); break; case 0x1f: /* fstpt mem */ gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fstt_ST0(tcg_ctx, cpu_env, cpu_A0); gen_helper_fpop(tcg_ctx, cpu_env); + fpu_update_ip(env); break; case 0x2c: /* frstor mem */ gen_update_cc_op(s); @@ -6251,21 +6254,25 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fbld_ST0(tcg_ctx, cpu_env, cpu_A0); + fpu_update_ip(env); break; case 0x3e: /* fbstp */ gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fbst_ST0(tcg_ctx, cpu_env, cpu_A0); gen_helper_fpop(tcg_ctx, cpu_env); + fpu_update_ip(env); break; case 0x3d: /* fildll */ tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); gen_helper_fildll_ST0(tcg_ctx, cpu_env, cpu_tmp1_i64); + fpu_update_ip(env); break; case 0x3f: /* fistpll */ gen_helper_fistll_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env); tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); gen_helper_fpop(tcg_ctx, cpu_env); + fpu_update_ip(env); break; default: goto illegal_op; @@ -6580,6 +6587,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, default: goto illegal_op; } + fpu_update_ip(env); } break; /************************/ From feb8ced027b7f33bfca6795093b1206df4c2315a Mon Sep 17 00:00:00 2001 From: mothran Date: Fri, 28 Aug 2015 10:39:11 -0700 Subject: [PATCH 03/10] fixed the FPIP updates to correctly only work with non-control instructions and make sure the pc addr is correct --- qemu/target-i386/translate.c | 22 +++++++-------- regress/fpu_ip.py | 52 ++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 11 deletions(-) create mode 100755 regress/fpu_ip.py diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c index 5b4ccb25..fc8c66ef 100644 --- a/qemu/target-i386/translate.c +++ b/qemu/target-i386/translate.c @@ -248,9 +248,9 @@ static void gen_update_cc_op(DisasContext *s) } } -static void fpu_update_ip(CPUX86State *env) +static void fpu_update_ip(CPUX86State *env, target_ulong pc) { - env->fpip = env->eip; + env->fpip = pc; } #ifdef TARGET_X86_64 @@ -6115,7 +6115,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* fcomp needs pop */ gen_helper_fpop(tcg_ctx, cpu_env); } - fpu_update_ip(env); + fpu_update_ip(env, pc_start); } break; case 0x08: /* flds */ @@ -6200,7 +6200,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_fpop(tcg_ctx, cpu_env); break; } - fpu_update_ip(env); + fpu_update_ip(env, pc_start); break; case 0x0c: /* fldenv mem */ gen_update_cc_op(s); @@ -6226,14 +6226,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fldt_ST0(tcg_ctx, cpu_env, cpu_A0); - fpu_update_ip(env); + fpu_update_ip(env, pc_start); break; case 0x1f: /* fstpt mem */ gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fstt_ST0(tcg_ctx, cpu_env, cpu_A0); gen_helper_fpop(tcg_ctx, cpu_env); - fpu_update_ip(env); + fpu_update_ip(env, pc_start); break; case 0x2c: /* frstor mem */ gen_update_cc_op(s); @@ -6254,25 +6254,25 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fbld_ST0(tcg_ctx, cpu_env, cpu_A0); - fpu_update_ip(env); + fpu_update_ip(env, pc_start); break; case 0x3e: /* fbstp */ gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fbst_ST0(tcg_ctx, cpu_env, cpu_A0); gen_helper_fpop(tcg_ctx, cpu_env); - fpu_update_ip(env); + fpu_update_ip(env, pc_start); break; case 0x3d: /* fildll */ tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); gen_helper_fildll_ST0(tcg_ctx, cpu_env, cpu_tmp1_i64); - fpu_update_ip(env); + fpu_update_ip(env, pc_start); break; case 0x3f: /* fistpll */ gen_helper_fistll_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env); tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); gen_helper_fpop(tcg_ctx, cpu_env); - fpu_update_ip(env); + fpu_update_ip(env, pc_start); break; default: goto illegal_op; @@ -6587,7 +6587,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, default: goto illegal_op; } - fpu_update_ip(env); + fpu_update_ip(env, pc_start); } break; /************************/ diff --git a/regress/fpu_ip.py b/regress/fpu_ip.py new file mode 100755 index 00000000..ed8fec6b --- /dev/null +++ b/regress/fpu_ip.py @@ -0,0 +1,52 @@ +#!/usr/bin/python +from unicorn import * +from unicorn.x86_const import * +from capstone import * + +ESP = 0x2000 +PAGE_SIZE = 0x8000 + +# mov [esp], DWORD 0x37f +# fldcw [esp] +# fnop +# fnstenv [esp + 8] +# pop ecx +CODE = b'\xc7\x04\x24\x7f\x03\x00\x00\xd9\x2c\x24\xd9\xd0\xd9\x74\x24\x08\x59' + +class SimpleEngine: + def __init__(self): + self.capmd = Cs(CS_ARCH_X86, CS_MODE_32) + + def disas_single(self, data): + for i in self.capmd.disasm(data, 16): + print("\t%s\t%s" % (i.mnemonic, i.op_str)) + break + +disasm = SimpleEngine() + +def hook_code(uc, addr, size, user_data): + mem = uc.mem_read(addr, size) + print(" 0x%X:" % (addr)), + disasm.disas_single(str(mem)) + +def mem_reader(addr, size): + tmp = mu.mem_read(addr, size) + + for i in tmp: + print(" 0x%x" % i), + print("") + + +mu = Uc(UC_ARCH_X86, UC_MODE_32) + +mu.mem_map(0x0, PAGE_SIZE) +mu.mem_map(0x4000, PAGE_SIZE) +mu.mem_write(0x4000, CODE) +mu.reg_write(UC_X86_REG_ESP, ESP) +mu.hook_add(UC_HOOK_CODE, hook_code) + + +mu.emu_start(0x4000, 0, 0, 5) +esp = mu.reg_read(UC_X86_REG_ESP) +print("value at ESP [0x%X - 4]: " % esp) +mem_reader(esp + 14, 4) \ No newline at end of file From 5d6a478d119394e63e11f6e9a1cc3cf33b19198b Mon Sep 17 00:00:00 2001 From: mothran Date: Fri, 28 Aug 2015 23:46:15 -0700 Subject: [PATCH 04/10] added expect output to fpu_ip.py --- regress/fpu_ip.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/regress/fpu_ip.py b/regress/fpu_ip.py index ed8fec6b..77efa21b 100755 --- a/regress/fpu_ip.py +++ b/regress/fpu_ip.py @@ -4,7 +4,7 @@ from unicorn.x86_const import * from capstone import * ESP = 0x2000 -PAGE_SIZE = 0x8000 +PAGE_SIZE = 2 * 1024 * 1024 # mov [esp], DWORD 0x37f # fldcw [esp] @@ -40,7 +40,6 @@ def mem_reader(addr, size): mu = Uc(UC_ARCH_X86, UC_MODE_32) mu.mem_map(0x0, PAGE_SIZE) -mu.mem_map(0x4000, PAGE_SIZE) mu.mem_write(0x4000, CODE) mu.reg_write(UC_X86_REG_ESP, ESP) mu.hook_add(UC_HOOK_CODE, hook_code) @@ -49,4 +48,14 @@ mu.hook_add(UC_HOOK_CODE, hook_code) mu.emu_start(0x4000, 0, 0, 5) esp = mu.reg_read(UC_X86_REG_ESP) print("value at ESP [0x%X - 4]: " % esp) -mem_reader(esp + 14, 4) \ No newline at end of file +mem_reader(esp + 14, 4) + +# EXPECTED OUTPUT: +# 0x4000: mov dword ptr [esp], 0x37f +# 0x4007: fldcw word ptr [esp] +# 0x400A: fnop +# 0x400C: fnstenv dword ptr [esp + 8] +# 0x4010: pop ecx +# value at ESP [0x2004 - 4]: +# 0x0 0x0 0xa 0x40 +# ^ this value should match the fnop instuction addr \ No newline at end of file From b7d60313b5ccd49e3a3d87c7190e011214089c60 Mon Sep 17 00:00:00 2001 From: mothran Date: Sat, 29 Aug 2015 01:56:36 -0700 Subject: [PATCH 05/10] added 64 bit mode to the fstenv helper function, also a fpu_ip64.py regress script --- qemu/target-i386/fpu_helper.c | 19 +++++++++-- regress/fpu_ip64.py | 62 +++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 2 deletions(-) create mode 100644 regress/fpu_ip64.py diff --git a/qemu/target-i386/fpu_helper.c b/qemu/target-i386/fpu_helper.c index fa20b7a1..a54580c8 100644 --- a/qemu/target-i386/fpu_helper.c +++ b/qemu/target-i386/fpu_helper.c @@ -986,7 +986,18 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) } } } - if (data32) { + switch (env->uc->mode) { + case (UC_MODE_64): + /* 64 bit */ + cpu_stl_data(env, ptr, env->fpuc); + cpu_stl_data(env, ptr + 4, fpus); + cpu_stl_data(env, ptr + 8, fptag); + cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */ + cpu_stl_data(env, ptr + 20, 0); /* fpcs */ + cpu_stl_data(env, ptr + 24, 0); /* fpoo */ + cpu_stl_data(env, ptr + 28, 0); /* fpos */ + break; + case (UC_MODE_32): /* 32 bit */ cpu_stl_data(env, ptr, env->fpuc); cpu_stl_data(env, ptr + 4, fpus); @@ -995,7 +1006,8 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) cpu_stl_data(env, ptr + 16, 0); /* fpcs */ cpu_stl_data(env, ptr + 20, 0); /* fpoo */ cpu_stl_data(env, ptr + 24, 0); /* fpos */ - } else { + break; + case (UC_MODE_16): /* 16 bit */ cpu_stw_data(env, ptr, env->fpuc); cpu_stw_data(env, ptr + 2, fpus); @@ -1004,6 +1016,9 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) cpu_stw_data(env, ptr + 8, 0); cpu_stw_data(env, ptr + 10, 0); cpu_stw_data(env, ptr + 12, 0); + break; + default: + break; } } diff --git a/regress/fpu_ip64.py b/regress/fpu_ip64.py new file mode 100644 index 00000000..dd0b5c1c --- /dev/null +++ b/regress/fpu_ip64.py @@ -0,0 +1,62 @@ +#!/usr/bin/python +from unicorn import * +from unicorn.x86_const import * +from capstone import * + +ESP = 0x2000 +PAGE_SIZE = 2 * 1024 * 1024 + +# mov [esp], DWORD 0x37f +# fldcw [esp] +# fnop +# fnstenv [esp + 8] +# pop ecx +CODE = "C704247F030000D92C24D9D0D974240859".decode('hex') + +class SimpleEngine: + def __init__(self): + self.capmd = Cs(CS_ARCH_X86, CS_MODE_64) + + def disas_single(self, data): + for i in self.capmd.disasm(data, 16): + print("\t%s\t%s" % (i.mnemonic, i.op_str)) + break + +disasm = SimpleEngine() + +def hook_code(uc, addr, size, user_data): + mem = uc.mem_read(addr, size) + print(" 0x%X:" % (addr)), + disasm.disas_single(str(mem)) + +def mem_reader(addr, size): + tmp = mu.mem_read(addr, size) + + for i in tmp: + print(" 0x%x" % i), + print("") + + +mu = Uc(UC_ARCH_X86, UC_MODE_64) + +mu.mem_map(0x0, PAGE_SIZE) +mu.mem_write(0x4000, CODE) +mu.reg_write(UC_X86_REG_RSP, ESP) +mu.hook_add(UC_HOOK_CODE, hook_code) + + +mu.emu_start(0x4000, 0, 0, 5) +rsp = mu.reg_read(UC_X86_REG_RSP) +print("Value of FPIP: [0x%X]" % (rsp + 10)) +mem_reader(rsp + 10, 8) +# EXPECTED OUTPUT: + +# 0x4000: mov dword ptr [rsp], 0x37f +# 0x4007: fldcw word ptr [rsp] +# 0x400A: fnop +# 0x400C: fnstenv dword ptr [rsp + 8] +# 0x4010: pop rcx +# Value of FPIP: [0x2012] +# 0x0 0x0 0xa 0x40 0x0 0x0 0x0 0x0 + +# WHERE: the value of FPIP should be the address of fnop \ No newline at end of file From 912faf2c3cb9c47977d115cdcd893d0894703946 Mon Sep 17 00:00:00 2001 From: mothran Date: Sun, 30 Aug 2015 18:04:28 -0700 Subject: [PATCH 06/10] after closer review, in x64 the the op size is 32 so data32 is set, can removed the unicorn dependency and regress/fpu_ip64.py still works --- qemu/target-i386/fpu_helper.c | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/qemu/target-i386/fpu_helper.c b/qemu/target-i386/fpu_helper.c index a54580c8..ea0c1fca 100644 --- a/qemu/target-i386/fpu_helper.c +++ b/qemu/target-i386/fpu_helper.c @@ -986,18 +986,7 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) } } } - switch (env->uc->mode) { - case (UC_MODE_64): - /* 64 bit */ - cpu_stl_data(env, ptr, env->fpuc); - cpu_stl_data(env, ptr + 4, fpus); - cpu_stl_data(env, ptr + 8, fptag); - cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */ - cpu_stl_data(env, ptr + 20, 0); /* fpcs */ - cpu_stl_data(env, ptr + 24, 0); /* fpoo */ - cpu_stl_data(env, ptr + 28, 0); /* fpos */ - break; - case (UC_MODE_32): + if (data32) { /* 32 bit */ cpu_stl_data(env, ptr, env->fpuc); cpu_stl_data(env, ptr + 4, fpus); @@ -1006,19 +995,15 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) cpu_stl_data(env, ptr + 16, 0); /* fpcs */ cpu_stl_data(env, ptr + 20, 0); /* fpoo */ cpu_stl_data(env, ptr + 24, 0); /* fpos */ - break; - case (UC_MODE_16): + } else { /* 16 bit */ cpu_stw_data(env, ptr, env->fpuc); cpu_stw_data(env, ptr + 2, fpus); cpu_stw_data(env, ptr + 4, fptag); - cpu_stw_data(env, ptr + 6, 0); + cpu_stw_data(env, ptr + 6, env->fpip); cpu_stw_data(env, ptr + 8, 0); cpu_stw_data(env, ptr + 10, 0); cpu_stw_data(env, ptr + 12, 0); - break; - default: - break; } } From 4cd5fa3811315ac5df1f20d42d628a180eafce15 Mon Sep 17 00:00:00 2001 From: mothran Date: Sun, 30 Aug 2015 18:56:55 -0700 Subject: [PATCH 07/10] fpip x64 fxsave working with using hflags to check CPU mode --- qemu/target-i386/fpu_helper.c | 44 ++++++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/qemu/target-i386/fpu_helper.c b/qemu/target-i386/fpu_helper.c index ea0c1fca..12d7710c 100644 --- a/qemu/target-i386/fpu_helper.c +++ b/qemu/target-i386/fpu_helper.c @@ -986,25 +986,41 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) } } } - if (data32) { - /* 32 bit */ +#ifdef TARGET_X86_64 + // DFLAG enum: tcg.h, case here to int + if (env->hflags & HF_CS64_MASK) { + printf("HELLO\n"); cpu_stl_data(env, ptr, env->fpuc); cpu_stl_data(env, ptr + 4, fpus); cpu_stl_data(env, ptr + 8, fptag); cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */ - cpu_stl_data(env, ptr + 16, 0); /* fpcs */ - cpu_stl_data(env, ptr + 20, 0); /* fpoo */ - cpu_stl_data(env, ptr + 24, 0); /* fpos */ - } else { - /* 16 bit */ - cpu_stw_data(env, ptr, env->fpuc); - cpu_stw_data(env, ptr + 2, fpus); - cpu_stw_data(env, ptr + 4, fptag); - cpu_stw_data(env, ptr + 6, env->fpip); - cpu_stw_data(env, ptr + 8, 0); - cpu_stw_data(env, ptr + 10, 0); - cpu_stw_data(env, ptr + 12, 0); + cpu_stl_data(env, ptr + 20, 0); /* fpcs */ + cpu_stl_data(env, ptr + 24, 0); /* fpoo */ + cpu_stl_data(env, ptr + 28, 0); /* fpos */ } +#endif + if (!(env->hflags & HF_CS64_MASK)) + { + if (data32) { + /* 32 bit */ + cpu_stl_data(env, ptr, env->fpuc); + cpu_stl_data(env, ptr + 4, fpus); + cpu_stl_data(env, ptr + 8, fptag); + cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */ + cpu_stl_data(env, ptr + 16, 0); /* fpcs */ + cpu_stl_data(env, ptr + 20, 0); /* fpoo */ + cpu_stl_data(env, ptr + 24, 0); /* fpos */ + } else { + /* 16 bit */ + cpu_stw_data(env, ptr, env->fpuc); + cpu_stw_data(env, ptr + 2, fpus); + cpu_stw_data(env, ptr + 4, fptag); + cpu_stw_data(env, ptr + 6, env->fpip); + cpu_stw_data(env, ptr + 8, 0); + cpu_stw_data(env, ptr + 10, 0); + cpu_stw_data(env, ptr + 12, 0); + } + } void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32) From 2b6f80675959fa4175d61b8e090e75859ad2bb96 Mon Sep 17 00:00:00 2001 From: mothran Date: Sun, 30 Aug 2015 19:22:41 -0700 Subject: [PATCH 08/10] removed testing printf --- qemu/target-i386/fpu_helper.c | 1 - 1 file changed, 1 deletion(-) diff --git a/qemu/target-i386/fpu_helper.c b/qemu/target-i386/fpu_helper.c index 12d7710c..3dbba049 100644 --- a/qemu/target-i386/fpu_helper.c +++ b/qemu/target-i386/fpu_helper.c @@ -989,7 +989,6 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) #ifdef TARGET_X86_64 // DFLAG enum: tcg.h, case here to int if (env->hflags & HF_CS64_MASK) { - printf("HELLO\n"); cpu_stl_data(env, ptr, env->fpuc); cpu_stl_data(env, ptr + 4, fpus); cpu_stl_data(env, ptr + 8, fptag); From e1ab761e8a2f8303775042ba44c69b533f571d41 Mon Sep 17 00:00:00 2001 From: mothran Date: Sun, 30 Aug 2015 19:32:39 -0700 Subject: [PATCH 09/10] fixed typo --- qemu/target-i386/fpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/qemu/target-i386/fpu_helper.c b/qemu/target-i386/fpu_helper.c index 3dbba049..e9cbd7d0 100644 --- a/qemu/target-i386/fpu_helper.c +++ b/qemu/target-i386/fpu_helper.c @@ -1019,6 +1019,7 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) cpu_stw_data(env, ptr + 10, 0); cpu_stw_data(env, ptr + 12, 0); } + } } From 6aa2b73bea09aeff7e65efa9bd18ca51f84859e8 Mon Sep 17 00:00:00 2001 From: mothran Date: Sun, 30 Aug 2015 19:39:46 -0700 Subject: [PATCH 10/10] removed ifdef for x64 in fpu saving --- qemu/target-i386/fpu_helper.c | 43 ++++++++++++++++------------------- 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/qemu/target-i386/fpu_helper.c b/qemu/target-i386/fpu_helper.c index e9cbd7d0..a74380f0 100644 --- a/qemu/target-i386/fpu_helper.c +++ b/qemu/target-i386/fpu_helper.c @@ -986,7 +986,7 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) } } } -#ifdef TARGET_X86_64 + // DFLAG enum: tcg.h, case here to int if (env->hflags & HF_CS64_MASK) { cpu_stl_data(env, ptr, env->fpuc); @@ -996,29 +996,24 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) cpu_stl_data(env, ptr + 20, 0); /* fpcs */ cpu_stl_data(env, ptr + 24, 0); /* fpoo */ cpu_stl_data(env, ptr + 28, 0); /* fpos */ - } -#endif - if (!(env->hflags & HF_CS64_MASK)) - { - if (data32) { - /* 32 bit */ - cpu_stl_data(env, ptr, env->fpuc); - cpu_stl_data(env, ptr + 4, fpus); - cpu_stl_data(env, ptr + 8, fptag); - cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */ - cpu_stl_data(env, ptr + 16, 0); /* fpcs */ - cpu_stl_data(env, ptr + 20, 0); /* fpoo */ - cpu_stl_data(env, ptr + 24, 0); /* fpos */ - } else { - /* 16 bit */ - cpu_stw_data(env, ptr, env->fpuc); - cpu_stw_data(env, ptr + 2, fpus); - cpu_stw_data(env, ptr + 4, fptag); - cpu_stw_data(env, ptr + 6, env->fpip); - cpu_stw_data(env, ptr + 8, 0); - cpu_stw_data(env, ptr + 10, 0); - cpu_stw_data(env, ptr + 12, 0); - } + } else if (data32) { + /* 32 bit */ + cpu_stl_data(env, ptr, env->fpuc); + cpu_stl_data(env, ptr + 4, fpus); + cpu_stl_data(env, ptr + 8, fptag); + cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */ + cpu_stl_data(env, ptr + 16, 0); /* fpcs */ + cpu_stl_data(env, ptr + 20, 0); /* fpoo */ + cpu_stl_data(env, ptr + 24, 0); /* fpos */ + } else { + /* 16 bit */ + cpu_stw_data(env, ptr, env->fpuc); + cpu_stw_data(env, ptr + 2, fpus); + cpu_stw_data(env, ptr + 4, fptag); + cpu_stw_data(env, ptr + 6, env->fpip); + cpu_stw_data(env, ptr + 8, 0); + cpu_stw_data(env, ptr + 10, 0); + cpu_stw_data(env, ptr + 12, 0); } }