Added cache flush after code patching in unit tests for arm64 and riscv
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549274f44c
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@ -78,6 +78,7 @@ static void test_arm64_code_patching() {
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OK(uc_close(uc));
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OK(uc_close(uc));
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}
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}
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// Need to flush the cache before running the emulation after patching
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static void test_arm64_code_patching_count() {
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static void test_arm64_code_patching_count() {
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uc_engine *uc;
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uc_engine *uc;
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char code[] = "\x00\x04\x00\x11"; // add w0, w0, 0x1
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char code[] = "\x00\x04\x00\x11"; // add w0, w0, 0x1
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@ -93,6 +94,7 @@ static void test_arm64_code_patching_count() {
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// patch instruction
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// patch instruction
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char patch_code[] = "\x00\xfc\x1f\x11"; // add w0, w0, 0x7FF
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char patch_code[] = "\x00\xfc\x1f\x11"; // add w0, w0, 0x7FF
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OK(uc_mem_write(uc, code_start, patch_code, sizeof(patch_code) - 1));
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OK(uc_mem_write(uc, code_start, patch_code, sizeof(patch_code) - 1));
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OK(uc_ctl_remove_cache(uc, code_start, code_start + sizeof(patch_code) - 1));
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// zero out x0
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// zero out x0
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r_x0 = 0x0;
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r_x0 = 0x0;
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OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0));
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OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0));
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@ -399,6 +399,7 @@ static void test_riscv64_code_patching() {
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OK(uc_close(uc));
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OK(uc_close(uc));
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}
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}
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// Need to flush the cache before running the emulation after patching
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static void test_riscv64_code_patching_count() {
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static void test_riscv64_code_patching_count() {
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uc_engine *uc;
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uc_engine *uc;
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char code[] = "\x93\x82\x12\x00"; // addi t0, t0, 0x1
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char code[] = "\x93\x82\x12\x00"; // addi t0, t0, 0x1
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@ -414,6 +415,7 @@ static void test_riscv64_code_patching_count() {
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// patch instruction
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// patch instruction
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char patch_code[] = "\x93\x82\xf2\x7f"; // addi t0, t0, 0x7FF
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char patch_code[] = "\x93\x82\xf2\x7f"; // addi t0, t0, 0x7FF
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OK(uc_mem_write(uc, code_start, patch_code, sizeof(patch_code) - 1));
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OK(uc_mem_write(uc, code_start, patch_code, sizeof(patch_code) - 1));
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OK(uc_ctl_remove_cache(uc, code_start, code_start + sizeof(patch_code) - 1));
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// zero out t0
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// zero out t0
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r_t0 = 0x0;
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r_t0 = 0x0;
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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