2015-08-21 10:04:50 +03:00
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#!/usr/bin/python
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from unicorn import *
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from unicorn.x86_const import *
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from unicorn.arm_const import *
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2015-09-17 23:45:15 +03:00
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import regress
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2015-08-21 10:04:50 +03:00
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# adds r1, #0x48
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# ldrsb r7, [r7, r7]
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# ldrsh r7, [r2, r1]
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# ldr r0, [pc, #0x168]
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# cmp r7, #0xbf
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# str r7, [r5, #0x20]
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# ldr r1, [r5, #0x64]
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# strb r7, [r5, #0xc]
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# ldr r0, [pc, #0x1a0]
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binary1 = b'\x48\x31\xff\x57\x57\x5e\x5a\x48\xbf\x2f\x2f\x62\x69\x6e\x2f\x73\x68\x48\xc1\xef\x08\x57\x54\x5f\x6a\x3b\x58\x0f\x05'
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2015-09-17 23:45:15 +03:00
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# binary1 = b'\x48\x31\xff\x57'
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2015-08-21 10:04:50 +03:00
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#adds r1, #0x48
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#ldrsb r7, [r7, r7]
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2015-09-17 23:45:15 +03:00
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class WrongRIPArm(regress.RegressTest):
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def runTest(self):
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mu = Uc(UC_ARCH_ARM, UC_MODE_THUMB)
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mu.mem_map(0, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(0, binary1)
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mu.reg_write(UC_ARM_REG_R13, 1 * 1024 * 1024)
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# emu for maximum 1 instruction.
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mu.emu_start(0, len(binary1), 0, 1)
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self.assertEqual(0x48, mu.reg_read(UC_ARM_REG_R1))
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pos = mu.reg_read(UC_ARM_REG_R15)
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self.assertEqual(0x2, pos)
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if __name__ == '__main__':
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regress.main()
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