2015-09-08 04:14:22 +03:00
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#!/usr/bin/python
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2015-09-08 04:07:28 +03:00
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from unicorn import *
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from unicorn.sparc_const import *
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2015-09-15 07:23:42 +03:00
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PAGE_SIZE = 1 * 1024 * 1024
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2015-09-11 09:02:27 +03:00
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uc = Uc(UC_ARCH_SPARC, UC_MODE_32)
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2015-09-08 04:07:28 +03:00
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uc.reg_write(UC_SPARC_REG_SP, 100)
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2015-09-15 07:23:42 +03:00
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uc.reg_write(UC_SPARC_REG_FP, 200)
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2015-09-16 11:46:10 +03:00
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# 0x0: \x80\x00\x20\x01 add %g0, 1, %g0
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# 0x4: \x82\x00\x60\x01 add %g1, 1, %g1
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# 0x8: \x84\x00\xA0\x01 add %g2, 1, %g2
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# 0xc: \x86\x00\xE0\x01 add %g3, 1, %g3
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# 0x10: \x88\x01\x20\x01 add %g4, 1, %g4
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# 0x14: \x8A\x01\x60\x01 add %g5, 1, %g5
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# 0x18: \x8C\x01\xA0\x01 add %g6, 1, %g6
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# 0x1c: \x8E\x01\xE0\x01 add %g7, 1, %g7
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# 0x20: \x90\x02\x20\x01 add %o0, 1, %o0
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# 0x24: \x92\x02\x60\x01 add %o1, 1, %o1
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# 0x28: \x94\x02\xA0\x01 add %o2, 1, %o2
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# 0x2c: \x96\x02\xE0\x01 add %o3, 1, %o3
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# 0x30: \x98\x03\x20\x01 add %o4, 1, %o4
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# 0x34: \x9A\x03\x60\x01 add %o5, 1, %o5
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# 0x38: \x9C\x03\xA0\x01 add %sp, 1, %sp
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# 0x3c: \x9E\x03\xE0\x01 add %o7, 1, %o7
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# 0x40: \xA0\x04\x20\x01 add %l0, 1, %l0
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# 0x44: \xA2\x04\x60\x01 add %l1, 1, %l1
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# 0x48: \xA4\x04\xA0\x01 add %l2, 1, %l2
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# 0x4c: \xA6\x04\xE0\x01 add %l3, 1, %l3
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# 0x50: \xA8\x05\x20\x01 add %l4, 1, %l4
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# 0x54: \xAA\x05\x60\x01 add %l5, 1, %l5
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# 0x58: \xAC\x05\xA0\x01 add %l6, 1, %l6
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# 0x5c: \xAE\x05\xE0\x01 add %l7, 1, %l7
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# 0x0: \xB0\x06\x20\x01 add %i0, 1, %i0
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# 0x4: \xB2\x06\x60\x01 add %i1, 1, %i1
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# 0x8: \xB4\x06\xA0\x01 add %i2, 1, %i2
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# 0xc: \xB6\x06\xE0\x01 add %i3, 1, %i3
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# 0x10: \xB8\x07\x20\x01 add %i4, 1, %i4
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# 0x14: \xBA\x07\x60\x01 add %i5, 1, %i5
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# 0x18: \xBC\x07\xA0\x01 add %fp, 1, %fp
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# 0x1c: \xBE\x07\xE0\x01 add %i7, 1, %i7
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2015-09-15 09:28:09 +03:00
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2015-09-15 09:05:33 +03:00
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CODE = "\x80\x00\x20\x01" \
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2015-09-16 11:46:10 +03:00
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"\x82\x00\x60\x01" \
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"\x84\x00\xA0\x01" \
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"\x86\x00\xE0\x01" \
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"\x88\x01\x20\x01" \
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"\x8A\x01\x60\x01" \
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"\x8C\x01\xA0\x01" \
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"\x8E\x01\xE0\x01" \
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"\x90\x02\x20\x01" \
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"\x92\x02\x60\x01" \
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"\x94\x02\xA0\x01" \
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"\x96\x02\xE0\x01" \
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"\x98\x03\x20\x01" \
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"\x9A\x03\x60\x01" \
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"\x9C\x03\xA0\x01" \
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"\x9E\x03\xE0\x01" \
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"\xA0\x04\x20\x01" \
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"\xA2\x04\x60\x01" \
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"\xA4\x04\xA0\x01" \
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"\xA6\x04\xE0\x01" \
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"\xA8\x05\x20\x01" \
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"\xAA\x05\x60\x01" \
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"\xAC\x05\xA0\x01" \
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"\xAE\x05\xE0\x01" \
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"\xB0\x06\x20\x01" \
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"\xB2\x06\x60\x01" \
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"\xB4\x06\xA0\x01" \
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"\xB6\x06\xE0\x01" \
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"\xB8\x07\x20\x01" \
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"\xBA\x07\x60\x01" \
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"\xBC\x07\xA0\x01" \
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"\xBE\x07\xE0\x01"
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2015-09-15 09:28:09 +03:00
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2015-09-15 07:23:42 +03:00
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uc.mem_map(0, PAGE_SIZE)
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2015-09-15 09:05:33 +03:00
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uc.mem_write(0, CODE)
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2015-09-15 09:28:09 +03:00
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uc.emu_start(0, len(CODE), 0, 32)
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2015-09-15 07:23:42 +03:00
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def print_registers(mu):
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2015-09-16 11:46:10 +03:00
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g0 = mu.reg_read(UC_SPARC_REG_G0)
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g1 = mu.reg_read(UC_SPARC_REG_G1)
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g2 = mu.reg_read(UC_SPARC_REG_G2)
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g3 = mu.reg_read(UC_SPARC_REG_G3)
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g4 = mu.reg_read(UC_SPARC_REG_G4)
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g5 = mu.reg_read(UC_SPARC_REG_G5)
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g6 = mu.reg_read(UC_SPARC_REG_G6)
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g7 = mu.reg_read(UC_SPARC_REG_G7)
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o0 = mu.reg_read(UC_SPARC_REG_O0)
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o1 = mu.reg_read(UC_SPARC_REG_O1)
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o2 = mu.reg_read(UC_SPARC_REG_O2)
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o3 = mu.reg_read(UC_SPARC_REG_O3)
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o4 = mu.reg_read(UC_SPARC_REG_O4)
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o5 = mu.reg_read(UC_SPARC_REG_O5)
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o6 = mu.reg_read(UC_SPARC_REG_O6)
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o7 = mu.reg_read(UC_SPARC_REG_O7)
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l0 = mu.reg_read(UC_SPARC_REG_L0)
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l1 = mu.reg_read(UC_SPARC_REG_L1)
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l2 = mu.reg_read(UC_SPARC_REG_L2)
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l3 = mu.reg_read(UC_SPARC_REG_L3)
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l4 = mu.reg_read(UC_SPARC_REG_L4)
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l5 = mu.reg_read(UC_SPARC_REG_L5)
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l6 = mu.reg_read(UC_SPARC_REG_L6)
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l7 = mu.reg_read(UC_SPARC_REG_L7)
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i0 = mu.reg_read(UC_SPARC_REG_I0)
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i1 = mu.reg_read(UC_SPARC_REG_I1)
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i2 = mu.reg_read(UC_SPARC_REG_I2)
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i3 = mu.reg_read(UC_SPARC_REG_I3)
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i4 = mu.reg_read(UC_SPARC_REG_I4)
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i5 = mu.reg_read(UC_SPARC_REG_I5)
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i6 = mu.reg_read(UC_SPARC_REG_I6)
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i7 = mu.reg_read(UC_SPARC_REG_I7)
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pc = mu.reg_read(UC_SPARC_REG_PC)
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sp = mu.reg_read(UC_SPARC_REG_SP)
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fp = mu.reg_read(UC_SPARC_REG_FP)
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print(" G0 = %d" % g0)
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print(" G1 = %d" % g1)
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print(" G2 = %d" % g2)
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print(" G3 = %d" % g3)
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print(" G4 = %d" % g4)
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print(" G5 = %d" % g5)
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print(" G6 = %d" % g6)
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print(" G7 = %d" % g7)
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print("")
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print(" O0 = %d" % o0)
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print(" O1 = %d" % o1)
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print(" O2 = %d" % o2)
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print(" O3 = %d" % o3)
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print(" O4 = %d" % o4)
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print(" O5 = %d" % o5)
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print(" O6 = %d" % o6)
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print(" O7 = %d" % o7)
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print("")
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print(" L0 = %d" % l0)
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print(" L1 = %d" % l1)
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print(" L2 = %d" % l2)
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print(" L3 = %d" % l3)
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print(" L4 = %d" % l4)
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print(" L5 = %d" % l5)
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print(" L6 = %d" % l6)
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print(" L7 = %d" % l7)
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print("")
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print(" I0 = %d" % i0)
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print(" I1 = %d" % i1)
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print(" I2 = %d" % i2)
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print(" I3 = %d" % i3)
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print(" I4 = %d" % i4)
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print(" I5 = %d" % i5)
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print(" I6 = %d" % i6)
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print(" I7 = %d" % i7)
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print("")
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print(" PC = %d" % pc)
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print(" SP = %d" % sp)
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print(" FP = %d" % fp)
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print("")
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2015-09-15 07:23:42 +03:00
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print_registers(uc)
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2015-09-15 09:28:09 +03:00
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assert uc.reg_read(UC_SPARC_REG_PC) == 128 # make sure we executed all instructions
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2015-09-15 09:05:33 +03:00
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assert uc.reg_read(UC_SPARC_REG_SP) == 101
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2015-09-15 09:28:09 +03:00
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assert uc.reg_read(UC_SPARC_REG_FP) == 201
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2015-09-15 07:23:42 +03:00
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2015-09-15 09:05:33 +03:00
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assert uc.reg_read(UC_SPARC_REG_G0) == 0 # G0 is always zero
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assert uc.reg_read(UC_SPARC_REG_G1) == 1
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assert uc.reg_read(UC_SPARC_REG_G2) == 1
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assert uc.reg_read(UC_SPARC_REG_G3) == 1
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assert uc.reg_read(UC_SPARC_REG_G4) == 1
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assert uc.reg_read(UC_SPARC_REG_G5) == 1
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assert uc.reg_read(UC_SPARC_REG_G6) == 1
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assert uc.reg_read(UC_SPARC_REG_G7) == 1
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assert uc.reg_read(UC_SPARC_REG_O0) == 1
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assert uc.reg_read(UC_SPARC_REG_O1) == 1
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assert uc.reg_read(UC_SPARC_REG_O2) == 1
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assert uc.reg_read(UC_SPARC_REG_O3) == 1
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assert uc.reg_read(UC_SPARC_REG_O4) == 1
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assert uc.reg_read(UC_SPARC_REG_O5) == 1
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assert uc.reg_read(UC_SPARC_REG_O6) == 101
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assert uc.reg_read(UC_SPARC_REG_O7) == 1
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assert uc.reg_read(UC_SPARC_REG_L0) == 1
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assert uc.reg_read(UC_SPARC_REG_L1) == 1
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assert uc.reg_read(UC_SPARC_REG_L2) == 1
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assert uc.reg_read(UC_SPARC_REG_L3) == 1
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assert uc.reg_read(UC_SPARC_REG_L4) == 1
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assert uc.reg_read(UC_SPARC_REG_L5) == 1
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assert uc.reg_read(UC_SPARC_REG_L6) == 1
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assert uc.reg_read(UC_SPARC_REG_L7) == 1
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2015-09-15 09:28:09 +03:00
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assert uc.reg_read(UC_SPARC_REG_I0) == 1
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assert uc.reg_read(UC_SPARC_REG_I1) == 1
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assert uc.reg_read(UC_SPARC_REG_I2) == 1
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assert uc.reg_read(UC_SPARC_REG_I3) == 1
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assert uc.reg_read(UC_SPARC_REG_I4) == 1
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assert uc.reg_read(UC_SPARC_REG_I5) == 1
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assert uc.reg_read(UC_SPARC_REG_I6) == 201
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2015-09-16 11:46:10 +03:00
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assert uc.reg_read(UC_SPARC_REG_I7) == 1
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