python3 port, less subtle things

This commit is contained in:
George Hotz 2019-03-23 15:13:21 -07:00
parent 119245a0e2
commit c5b2fab9d9
5 changed files with 27 additions and 20 deletions

View File

@ -11,7 +11,7 @@ import struct
from PIL import Image
import base64
try:
import StringIO
from StringIO import StringIO
except ImportError:
from io import BytesIO as StringIO
@ -314,7 +314,7 @@ def guess_calling_conv(program,readregs,readstack):
return ('UNKNOWN',0) #we can't guess the ABI with 0 information
regs = program.tregs[0]
readregs = map(lambda x: regs[x], readregs) #convert read regs into strings
readregs = list(map(lambda x: regs[x], readregs)) #convert read regs into strings
for abi in filter(lambda x:x[0] != "_",static2.ABITYPE.__dict__):
if abi == 'UNKNOWN':
@ -365,14 +365,14 @@ def analyse_calls(trace):
seen = 0
init_regs = set()
uninit_regs = set()
for cl in xrange(clnum+1,endclnum):
for cl in range(clnum+1,endclnum):
changes = filter(lambda x:x['type'] in "LS",trace.db.fetch_changes_by_clnum(cl, -1))
argchanges = filter(lambda x:argrange[0] <= x['address'] <= argrange[1], changes)
argchanges = list(filter(lambda x:argrange[0] <= x['address'] <= argrange[1], changes))
if len(argchanges) > 0:
seen = max(max(map(lambda x:x['address'],argchanges)),seen)
rchanges = filter(lambda x:x['type'] in "RW",trace.db.fetch_changes_by_clnum(cl, -1))
for rchange in rchanges:
regnum = rchange['address']/rsize
regnum = rchange['address']//rsize
if rchange['type'] is 'W' and regnum < nregs:
init_regs.add(regnum)
if ((regnum) in uninit_regs) and (rchange['data'] == regs[regnum]):
@ -404,7 +404,7 @@ def display_call_args(instr,trace,clnum):
ret = []
i = 0
for i in xrange(min(nargs,len(args))):
for i in range(min(nargs,len(args))):
ret += [ghex(regs[program.tregs[0].index(args[i])])]
if len(args) > 0:
@ -413,7 +413,7 @@ def display_call_args(instr,trace,clnum):
if i < nargs:
stack_reg = ["ESP","RSP","SP"][["i386","x86-64","arm"].index(program.static['arch'])]
esp = regs[program.tregs[0].index(stack_reg)]
for j in xrange(i,nargs):
for j in range(i,nargs):
ret += [ghex(struct.unpack("<Q" if program.tregs[1] == 8 else "<I", \
trace.fetch_raw_memory(clnum, esp+program.tregs[1], program.tregs[1]))[0])]
esp += program.tregs[1]
@ -491,11 +491,11 @@ def get_vtimeline_picture(trace, minclnum, maxclnum):
if i/sampling < im_y:
px[0, i/sampling] = (96, 32, 32)
buf = StringIO.StringIO()
buf = StringIO()
im.save(buf, format='PNG')
dat = "data:image/png;base64,"+base64.b64encode(buf.getvalue())
return dat
dat = b"data:image/png;base64,"+base64.b64encode(buf.getvalue())
return dat.decode('utf-8')
def analyze(trace, program):
minclnum = trace.db.get_minclnum()

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@ -472,9 +472,9 @@ class Trace:
self.mapped.append(mapp)
try:
try:
f = open(os.environ['QEMU_LD_PREFIX']+"/"+files[fil])
f = open(os.environ['QEMU_LD_PREFIX']+"/"+files[fil], 'rb')
except:
f = open(files[fil])
f = open(files[fil], 'rb')
alldat = f.read()
if fxn == "mmap2":
@ -524,7 +524,7 @@ class Trace:
def load_base_memory(self):
def get_forkbase_from_log(n):
ret = struct.unpack("i", open(qira_config.TRACE_FILE_BASE+str(n)).read(0x18)[0x10:0x14])[0]
ret = struct.unpack("i", open(qira_config.TRACE_FILE_BASE+str(n), 'rb').read(0x18)[0x10:0x14])[0]
if ret == -1:
return n
else:
@ -533,7 +533,7 @@ class Trace:
try:
forkbase = get_forkbase_from_log(self.forknum)
print("*** using base %d for %d" % (forkbase, self.forknum))
f = open(qira_config.TRACE_FILE_BASE+str(forkbase)+"_base")
f = open(qira_config.TRACE_FILE_BASE+str(forkbase)+"_base", 'r')
except Exception as e:
print("*** base file issue",e)
# done
@ -580,11 +580,11 @@ class Trace:
try:
if fn in img_map:
off = max(i for i in img_map[fn].iter_keys() if i <= offset)
with open(img_map[fn][off]) as f:
with open(img_map[fn][off], 'rb') as f:
f.seek(offset-off)
dat = f.read(se-ss)
else:
with open(fn) as f:
with open(fn, 'rb') as f:
f.seek(offset)
dat = f.read(se-ss)
except Exception as e:

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@ -1,5 +1,6 @@
from __future__ import print_function
from qira_base import *
import traceback
import qira_config
import os
import sys
@ -27,6 +28,7 @@ def socket_method(func):
print("SOCKET %6.2f ms in %-20s with" % (tm, func.__name__), args)
return ret
except Exception as e:
traceback.print_exc()
print("ERROR",e,"in",func.__name__,"with",args)
return func_wrapper

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@ -265,7 +265,7 @@ class CsInsn(object):
raise Exception('arch "{}" not supported by capstone'.format(arch))
self.md.detail = True
try:
self.i = self.md.disasm(self.raw, self.address).next()
self.i = next(self.md.disasm(self.raw, self.address))
self.decoded = True
self.regs_read = self.i.regs_read
self.regs_write = self.i.regs_write
@ -446,7 +446,7 @@ class CsInsn(object):
#[a, +, b, -, c] -> sum(a, +b, -c)
if len(spl) > 2:
addr = _eval_op_x86(spl[0])
for i in xrange(1, len(spl), 2):
for i in range(1, len(spl), 2):
if spl[i] == "+":
addr += _eval_op_x86(spl[i+1])
else:

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@ -234,6 +234,11 @@ class Static:
# TODO: refactor this!
def memory(self, address, ln):
dat = []
def ret():
if (sys.version_info > (3, 0)):
return bytes(dat)
else:
return ''.join(dat)
for i in range(ln):
ri = address+i
@ -244,8 +249,8 @@ class Static:
dat.append(self.base_memory[(ss,se)][ri-ss])
break
except:
return ''.join(dat)
return ''.join(dat)
return ret()
return ret()
def add_memory_chunk(self, address, dat):
#print "add segment",hex(address),len(dat)