From bed9204678fed1cc260d16f9f2d576d84f025a90 Mon Sep 17 00:00:00 2001 From: Yahya Lmallas Date: Fri, 5 Feb 2016 01:19:32 +0100 Subject: [PATCH] This could be better one line instead of two --- middleware/arch.py | 14 +++++++------- middleware/qira_program.py | 6 ++---- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/middleware/arch.py b/middleware/arch.py index fe7158eb..5dcea5da 100644 --- a/middleware/arch.py +++ b/middleware/arch.py @@ -1,6 +1,6 @@ # (regname, regsize, is_big_endian, arch_name, branches) -# PowerPC CPU +# PowerPC CPU REGS PPCREGS = [[], 4, True, "ppc", ["bl "]] for i in range(32): PPCREGS[0].append("r"+str(i)) @@ -11,7 +11,7 @@ PPCREGS[0].append("ctr") for i in range(8): PPCREGS[0].append("cr"+str(i)) -# Aarch64 CPU +# Aarch64 CPU REGS AARCH64REGS = [[], 8, False, "aarch64", ["bl ", "blx "]] for i in range(8): AARCH64REGS[0].append(None) @@ -21,7 +21,7 @@ for i in range(32): AARCH64REGS[0][8+31] = "sp" AARCH64REGS[0].append("pc") -# MIPS CPU +# MIPS CPU REGS MIPSREGLIST = ['$zero', '$at', '$v0', '$v1', '$a0', '$a1', '$a2', '$a3'] for i in range(8): MIPSREGLIST.append('$t'+str(i)) @@ -38,12 +38,12 @@ MIPSREGLIST.append('$ra') MIPSREGLIST.append('$pc') MIPSREGS = [MIPSREGLIST, 4, True, "mips", ["jal\t","jr\t","jal","jr"]] -# ARM CPU -ARMREGS = [['R0','R1','R2','R3','R4','R5','R6','R7','R8','R9','R10','R11','IP','SP','LR','PC'], 4, False, "arm"] +# ARM CPU REGS +ARMREGS = [['R0','R1','R2','R3','R4','R5','R6','R7','R8','R9','R10','R11','IP','SP','LR','PC'], 4, False, "arm"] # FP = R7 If THUMB2 Mode enabled, & R11 If not. -# Intel x86 CPU +# Intel x86 CPU REGS X86REGS = [['EAX', 'ECX', 'EDX', 'EBX', 'ESP', 'EBP', 'ESI', 'EDI', 'EIP'], 4, False, "i386"] -# x86_64 CPU +# x86_64 CPU REGSZ X64REGS = [['RAX', 'RCX', 'RDX', 'RBX', 'RSP', 'RBP', 'RSI', 'RDI', "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", 'RIP'], 8, False, "x86-64"] diff --git a/middleware/qira_program.py b/middleware/qira_program.py index ff35f17e..0ac331b7 100644 --- a/middleware/qira_program.py +++ b/middleware/qira_program.py @@ -166,14 +166,12 @@ class Program: self.pintool = pin_dir + "obj-ia32/qirapin.so" elif self.fb == 0x800: use_lib('mips') - arch.MIPSREGS[2] = True - arch.MIPSREGS[3] = "mips" + arch.MIPSREGS[2:-1] = (True, "mips") self.tregs = arch.MIPSREGS self.qirabinary = qemu_dir + 'qira-mips' elif self.fb == 0x08: use_lib('mipsel') - arch.MIPSREGS[2] = False - arch.MIPSREGS[3] = "mipsel" + arch.MIPSREGS[2:-1] = (False, "mipsel") self.tregs = arch.MIPSREGS self.qirabinary = qemu_dir + 'qira-mipsel' elif self.fb == 0x1400: # big endian...