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Redefine REGS from tuples to lists to allow assignement for dynamic types to fix endianess etc...

This commit is contained in:
Yahya Lmallas 2016-02-05 00:15:34 +01:00
parent 9438c02f87
commit 6097bbc543
2 changed files with 23 additions and 9 deletions
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25
middleware/arch.py
View File

@ -1,16 +1,18 @@
# (regname, regsize, is_big_endian, arch_name, branches)
PPCREGS = ([], 4, True, "ppc", ["bl "])
# PowerPC CPU
PPCREGS = [[], 4, True, "ppc", ["bl "]]
for i in range(32):
PPCREGS[0].append("r"+str(i))
for i in range(32):
PPCREGS[0].append(None)
PPCREGS[0].append("lr")
PPCREGS[0].append("ctr")
for i in range(8):
PPCREGS[0].append("cr"+str(i))
AARCH64REGS = ([], 8, False, "aarch64", ["bl ", "blx "])
# Aarch64 CPU
AARCH64REGS = [[], 8, False, "aarch64", ["bl ", "blx "]]
for i in range(8):
AARCH64REGS[0].append(None)
for i in range(32):
@ -19,6 +21,7 @@ for i in range(32):
AARCH64REGS[0][8+31] = "sp"
AARCH64REGS[0].append("pc")
# MIPS CPU
MIPSREGLIST = ['$zero', '$at', '$v0', '$v1', '$a0', '$a1', '$a2', '$a3']
for i in range(8):
MIPSREGLIST.append('$t'+str(i))
@ -34,11 +37,15 @@ MIPSREGLIST.append('$fp')
MIPSREGLIST.append('$ra')
MIPSREGLIST.append('$pc')
MIPSREGS = (MIPSREGLIST, 4, True, "mips", ["jal\t","jr\t","jal","jr"])
MIPSELREGS = (MIPSREGLIST, 4, False, "mipsel", ["jal\t","jr\t","jal","jr"])
MIPSREGS = [MIPSREGLIST, 4, True, "mips", ["jal\t","jr\t","jal","jr"]]
MIPSELREGS = [MIPSREGLIST, 4, False, "mipsel", ["jal\t","jr\t","jal","jr"]]
# this stuff should be moved to static
ARMREGS = (['R0','R1','R2','R3','R4','R5','R6','R7','R8','R9','R10','R11','IP','SP','LR','PC'], 4, False, "arm")
X86REGS = (['EAX', 'ECX', 'EDX', 'EBX', 'ESP', 'EBP', 'ESI', 'EDI', 'EIP'], 4, False, "i386")
X64REGS = (['RAX', 'RCX', 'RDX', 'RBX', 'RSP', 'RBP', 'RSI', 'RDI', "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", 'RIP'], 8, False, "x86-64")
# ARM CPU
ARMREGS = [['R0','R1','R2','R3','R4','R5','R6','R7','R8','R9','R10','R11','IP','SP','LR','PC'], 4, False, "arm"]
# Intel x86 CPU
X86REGS = [['EAX', 'ECX', 'EDX', 'EBX', 'ESP', 'EBP', 'ESI', 'EDI', 'EIP'], 4, False, "i386"]
# x86_64 CPU
X64REGS = [['RAX', 'RCX', 'RDX', 'RBX', 'RSP', 'RBP', 'RSI', 'RDI', "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", 'RIP'], 8, False, "x86-64"]

7
middleware/qira_program.py
View File

@ -217,6 +217,9 @@ class Program:
if progdat[0x0:0x04] in (MACHO_P200_FAT_MAGIC, MACHO_P200_FAT_CIGAM):
raise NotImplementedError("Pack200 compressed files are not supported yet")
elif progdat[0x0:0x04] in (MACHO_FAT_MAGIC, MACHO_FAT_CIGAM):
if progdat[0x0:0x04] == MACHO_FAT_CIGAM:
arch.ARMREGS[2] = True
arch.AARCH64REGS[2] = True
if self.macharch == "arm":
self.tregs = arch.ARMREGS
self.pintool = ""
@ -251,6 +254,8 @@ class Program:
print "**** Mach-O X86/64 architecture detected"
if progdat[0x0:0x04] in (MACHO_MAGIC_64, MACHO_CIGAM_64):
if progdat[0x0:0x04] == MACHO_CIGAM_64:
arch.AARCH64REGS[2] = True
if self.macharch == "aarch64":
self.tregs = arch.AARCH64REGS
self.pintool = ""
@ -258,6 +263,8 @@ class Program:
self.tregs = arch.X64REGS
self.pintool = pin_dir + "obj-intel64/qirapin.dylib"
elif progdat[0x0:0x04] in (MACHO_MAGIC, MACHO_CIGAM):
if progdat[0x0:0x04] == MACHO_CIGAM:
arch.ARMREGS[2] = True
if self.macharch == "arm":
self.tregs = arch.ARMREGS
self.pintool = ""