Richard Henderson fffde6695f target/openrisc: Fix tlb flushing in mtspr ... The previous code was confused, avoiding the flush of the old entry if the new entry is invalid. We need to flush the old page if the old entry is valid and the new page if the new entry is valid. This bug was masked by over-flushing elsewhere. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>		2018-07-03 00:05:28 +09:00
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cpu.c	target/openrisc: Remove indirect function calls for mmu	2018-07-03 00:05:28 +09:00
cpu.h	target/openrisc: Reduce tlb to a single dimension	2018-07-03 00:05:28 +09:00
disas.c	target/openrisc: Add print_insn_or1k	2018-07-03 00:05:28 +09:00
exception_helper.c	misc: remove duplicated includes	2017-12-18 17:07:02 +03:00
exception.c
exception.h
fpu_helper.c	target-openrisc: Write back result before FPE exception	2018-05-14 14:35:02 -07:00
gdbstub.c	target/openrisc: implement shadow registers	2017-05-04 09:39:01 +09:00
helper.h	target/openrisc: Form the spr index from tcg	2018-07-03 00:05:28 +09:00
insns.decode	target/openrisc: Convert dec_float	2018-05-14 14:55:29 -07:00
interrupt_helper.c	target/openrisc: Remove indirect function calls for mmu	2018-07-03 00:05:28 +09:00
interrupt.c	target/openrisc: Remove indirect function calls for mmu	2018-07-03 00:05:28 +09:00
machine.c	target/openrisc: Reduce tlb to a single dimension	2018-07-03 00:05:28 +09:00
Makefile.objs	target/openrisc: Merge mmu_helper.c into mmu.c	2018-07-03 00:05:28 +09:00
mmu.c	target/openrisc: Reduce tlb to a single dimension	2018-07-03 00:05:28 +09:00
sys_helper.c	target/openrisc: Fix tlb flushing in mtspr	2018-07-03 00:05:28 +09:00
translate.c	target/openrisc: Form the spr index from tcg	2018-07-03 00:05:28 +09:00