39901aea06
For the AN547 image, the FPGAIO block has an extra DBGCTRL register, which is used to control the SPNIDEN, SPIDEN, NPIDEN and DBGEN inputs to the CPU. These signals control when the CPU permits use of the external debug interface. Our CPU models don't implement the external debug interface, so we model the register as reads-as-written. Implement the register, with a property defining whether it is present, and allow mps2-tz boards to specify that it is present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-39-peter.maydell@linaro.org
63 lines
1.5 KiB
C
63 lines
1.5 KiB
C
/*
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* ARM MPS2 FPGAIO emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the FPGAIO register block in the AN505
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* FPGA image for the MPS2 dev board; it is documented in the
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* application note:
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* https://developer.arm.com/documentation/dai0505/latest/
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*
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* QEMU interface:
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* + sysbus MMIO region 0: the register bank
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*/
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#ifndef MPS2_FPGAIO_H
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#define MPS2_FPGAIO_H
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#include "hw/sysbus.h"
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#include "hw/misc/led.h"
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#include "qom/object.h"
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#define TYPE_MPS2_FPGAIO "mps2-fpgaio"
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OBJECT_DECLARE_SIMPLE_TYPE(MPS2FPGAIO, MPS2_FPGAIO)
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#define MPS2FPGAIO_MAX_LEDS 32
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struct MPS2FPGAIO {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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LEDState *led[MPS2FPGAIO_MAX_LEDS];
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uint32_t num_leds;
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bool has_switches;
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bool has_dbgctrl;
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uint32_t led0;
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uint32_t prescale;
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uint32_t misc;
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uint32_t dbgctrl;
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/* QEMU_CLOCK_VIRTUAL time at which counter and pscntr were last synced */
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int64_t pscntr_sync_ticks;
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/* Values of COUNTER and PSCNTR at time pscntr_sync_ticks */
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uint32_t counter;
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uint32_t pscntr;
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uint32_t prescale_clk;
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/* These hold the CLOCK_VIRTUAL ns tick when the CLK1HZ/CLK100HZ was zero */
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int64_t clk1hz_tick_offset;
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int64_t clk100hz_tick_offset;
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};
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#endif
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