854123bf8d
The Aspeed SoC includes a set of watchdog timers using 32-bit decrement counters, which can be based either on the APB clock or a 1 MHz clock. The watchdog timer is designed to prevent system deadlock and, in general, it should be restarted before timeout. When a timeout occurs, different types of signals can be generated, ARM reset, SOC reset, System reset, CPU Interrupt, external signal or boot from alternate block. The current model only performs the system reset function as this is used by U-Boot and Linux. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 1485452251-1593-2-git-send-email-clg@kaod.org [clg: - fixed compile breakage - fixed io region size - added watchdog_perform_action() on timer expiry - wrote a commit log - merged fixes from Andrew Jeffery to scale the reload value ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33 lines
684 B
C
33 lines
684 B
C
/*
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* ASPEED Watchdog Controller
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*
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* Copyright (C) 2016-2017 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_WDT_H
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#define ASPEED_WDT_H
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_WDT "aspeed.wdt"
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#define ASPEED_WDT(obj) \
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OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
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#define ASPEED_WDT_REGS_MAX (0x20 / 4)
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typedef struct AspeedWDTState {
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/*< private >*/
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SysBusDevice parent_obj;
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QEMUTimer *timer;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t regs[ASPEED_WDT_REGS_MAX];
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uint32_t pclk_freq;
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} AspeedWDTState;
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#endif /* ASPEED_WDT_H */
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