5add35bec1
If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode (ICH9 will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO_REBOOT bit (CC: offset 0x3410:bit 5). The NO_REBOOT bit is set when SPKR pin on ICH9 is sampled high. This bit may be set or cleared by software if the strap is sampled low but may not override the strap when it indicates "No Reboot". This patch implements the logic where hardware has ability to set SPKR pin through a property named "noreboot" and it's sampled high by default. Signed-off-by: Paulo Alcantara <pcacjr@zytor.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
265 lines
7.4 KiB
C
265 lines
7.4 KiB
C
/*
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* QEMU ICH9 TCO emulation
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*
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* Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu-common.h"
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#include "sysemu/watchdog.h"
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#include "hw/i386/ich9.h"
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#include "hw/acpi/tco.h"
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//#define DEBUG
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#ifdef DEBUG
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#define TCO_DEBUG(fmt, ...) \
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do { \
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fprintf(stderr, "%s "fmt, __func__, ## __VA_ARGS__); \
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} while (0)
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#else
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#define TCO_DEBUG(fmt, ...) do { } while (0)
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#endif
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enum {
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TCO_RLD_DEFAULT = 0x0000,
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TCO_DAT_IN_DEFAULT = 0x00,
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TCO_DAT_OUT_DEFAULT = 0x00,
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TCO1_STS_DEFAULT = 0x0000,
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TCO2_STS_DEFAULT = 0x0000,
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TCO1_CNT_DEFAULT = 0x0000,
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TCO2_CNT_DEFAULT = 0x0008,
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TCO_MESSAGE1_DEFAULT = 0x00,
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TCO_MESSAGE2_DEFAULT = 0x00,
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TCO_WDCNT_DEFAULT = 0x00,
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TCO_TMR_DEFAULT = 0x0004,
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SW_IRQ_GEN_DEFAULT = 0x03,
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};
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static inline void tco_timer_reload(TCOIORegs *tr)
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{
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tr->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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((int64_t)(tr->tco.tmr & TCO_TMR_MASK) * TCO_TICK_NSEC);
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timer_mod(tr->tco_timer, tr->expire_time);
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}
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static inline void tco_timer_stop(TCOIORegs *tr)
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{
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tr->expire_time = -1;
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}
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static void tco_timer_expired(void *opaque)
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{
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TCOIORegs *tr = opaque;
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ICH9LPCPMRegs *pm = container_of(tr, ICH9LPCPMRegs, tco_regs);
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ICH9LPCState *lpc = container_of(pm, ICH9LPCState, pm);
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uint32_t gcs = pci_get_long(lpc->chip_config + ICH9_CC_GCS);
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tr->tco.rld = 0;
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tr->tco.sts1 |= TCO_TIMEOUT;
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if (++tr->timeouts_no == 2) {
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tr->tco.sts2 |= TCO_SECOND_TO_STS;
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tr->tco.sts2 |= TCO_BOOT_STS;
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tr->timeouts_no = 0;
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if (!lpc->pin_strap.spkr_hi && !(gcs & ICH9_CC_GCS_NO_REBOOT)) {
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watchdog_perform_action();
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tco_timer_stop(tr);
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return;
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}
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}
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if (pm->smi_en & ICH9_PMIO_SMI_EN_TCO_EN) {
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ich9_generate_smi();
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} else {
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ich9_generate_nmi();
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}
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tr->tco.rld = tr->tco.tmr;
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tco_timer_reload(tr);
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}
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/* NOTE: values of 0 or 1 will be ignored by ICH */
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static inline int can_start_tco_timer(TCOIORegs *tr)
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{
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return !(tr->tco.cnt1 & TCO_TMR_HLT) && tr->tco.tmr > 1;
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}
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static uint32_t tco_ioport_readw(TCOIORegs *tr, uint32_t addr)
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{
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uint16_t rld;
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switch (addr) {
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case TCO_RLD:
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if (tr->expire_time != -1) {
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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int64_t elapsed = (tr->expire_time - now) / TCO_TICK_NSEC;
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rld = (uint16_t)elapsed | (tr->tco.rld & ~TCO_RLD_MASK);
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} else {
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rld = tr->tco.rld;
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}
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return rld;
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case TCO_DAT_IN:
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return tr->tco.din;
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case TCO_DAT_OUT:
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return tr->tco.dout;
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case TCO1_STS:
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return tr->tco.sts1;
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case TCO2_STS:
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return tr->tco.sts2;
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case TCO1_CNT:
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return tr->tco.cnt1;
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case TCO2_CNT:
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return tr->tco.cnt2;
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case TCO_MESSAGE1:
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return tr->tco.msg1;
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case TCO_MESSAGE2:
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return tr->tco.msg2;
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case TCO_WDCNT:
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return tr->tco.wdcnt;
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case TCO_TMR:
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return tr->tco.tmr;
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case SW_IRQ_GEN:
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return tr->sw_irq_gen;
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}
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return 0;
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}
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static void tco_ioport_writew(TCOIORegs *tr, uint32_t addr, uint32_t val)
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{
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switch (addr) {
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case TCO_RLD:
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tr->timeouts_no = 0;
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if (can_start_tco_timer(tr)) {
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tr->tco.rld = tr->tco.tmr;
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tco_timer_reload(tr);
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} else {
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tr->tco.rld = val;
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}
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break;
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case TCO_DAT_IN:
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tr->tco.din = val;
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tr->tco.sts1 |= SW_TCO_SMI;
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ich9_generate_smi();
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break;
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case TCO_DAT_OUT:
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tr->tco.dout = val;
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tr->tco.sts1 |= TCO_INT_STS;
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/* TODO: cause an interrupt, as selected by the TCO_INT_SEL bits */
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break;
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case TCO1_STS:
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tr->tco.sts1 = val & TCO1_STS_MASK;
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break;
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case TCO2_STS:
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tr->tco.sts2 = val & TCO2_STS_MASK;
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break;
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case TCO1_CNT:
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val &= TCO1_CNT_MASK;
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/*
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* once TCO_LOCK bit is set, it can not be cleared by software. a reset
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* is required to change this bit from 1 to 0 -- it defaults to 0.
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*/
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tr->tco.cnt1 = val | (tr->tco.cnt1 & TCO_LOCK);
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if (can_start_tco_timer(tr)) {
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tr->tco.rld = tr->tco.tmr;
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tco_timer_reload(tr);
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} else {
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tco_timer_stop(tr);
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}
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break;
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case TCO2_CNT:
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tr->tco.cnt2 = val;
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break;
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case TCO_MESSAGE1:
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tr->tco.msg1 = val;
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break;
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case TCO_MESSAGE2:
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tr->tco.msg2 = val;
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break;
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case TCO_WDCNT:
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tr->tco.wdcnt = val;
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break;
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case TCO_TMR:
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tr->tco.tmr = val;
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break;
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case SW_IRQ_GEN:
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tr->sw_irq_gen = val;
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break;
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}
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}
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static uint64_t tco_io_readw(void *opaque, hwaddr addr, unsigned width)
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{
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TCOIORegs *tr = opaque;
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return tco_ioport_readw(tr, addr);
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}
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static void tco_io_writew(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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TCOIORegs *tr = opaque;
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tco_ioport_writew(tr, addr, val);
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}
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static const MemoryRegionOps tco_io_ops = {
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.read = tco_io_readw,
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.write = tco_io_writew,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 2,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent)
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{
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*tr = (TCOIORegs) {
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.tco = {
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.rld = TCO_RLD_DEFAULT,
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.din = TCO_DAT_IN_DEFAULT,
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.dout = TCO_DAT_OUT_DEFAULT,
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.sts1 = TCO1_STS_DEFAULT,
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.sts2 = TCO2_STS_DEFAULT,
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.cnt1 = TCO1_CNT_DEFAULT,
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.cnt2 = TCO2_CNT_DEFAULT,
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.msg1 = TCO_MESSAGE1_DEFAULT,
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.msg2 = TCO_MESSAGE2_DEFAULT,
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.wdcnt = TCO_WDCNT_DEFAULT,
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.tmr = TCO_TMR_DEFAULT,
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},
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.sw_irq_gen = SW_IRQ_GEN_DEFAULT,
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.tco_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tco_timer_expired, tr),
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.expire_time = -1,
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.timeouts_no = 0,
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};
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memory_region_init_io(&tr->io, memory_region_owner(parent),
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&tco_io_ops, tr, "sm-tco", ICH9_PMIO_TCO_LEN);
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memory_region_add_subregion(parent, ICH9_PMIO_TCO_RLD, &tr->io);
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}
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const VMStateDescription vmstate_tco_io_sts = {
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.name = "tco io device status",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT16(tco.rld, TCOIORegs),
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VMSTATE_UINT8(tco.din, TCOIORegs),
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VMSTATE_UINT8(tco.dout, TCOIORegs),
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VMSTATE_UINT16(tco.sts1, TCOIORegs),
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VMSTATE_UINT16(tco.sts2, TCOIORegs),
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VMSTATE_UINT16(tco.cnt1, TCOIORegs),
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VMSTATE_UINT16(tco.cnt2, TCOIORegs),
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VMSTATE_UINT8(tco.msg1, TCOIORegs),
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VMSTATE_UINT8(tco.msg2, TCOIORegs),
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VMSTATE_UINT8(tco.wdcnt, TCOIORegs),
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VMSTATE_UINT16(tco.tmr, TCOIORegs),
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VMSTATE_UINT8(sw_irq_gen, TCOIORegs),
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VMSTATE_TIMER_PTR(tco_timer, TCOIORegs),
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VMSTATE_INT64(expire_time, TCOIORegs),
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VMSTATE_UINT8(timeouts_no, TCOIORegs),
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VMSTATE_END_OF_LIST()
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}
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};
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