60d30cff84
SPRC/SPRD were recently added to all BookS CPUs supported, but they are only tested on POWER9 and POWER10, so restrict them to those CPUs. SPR indirect scratch registers presently replicated per-CPU like SMT SPRs, but the PnvCore is a better place for them since they are restricted to P9/P10. Also add SPR indirect read access to core thread state for POWER9 since skiboot accesses that when booting to check for big-core mode. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
495 lines
14 KiB
C
495 lines
14 KiB
C
/*
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* Miscellaneous PowerPC emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "qemu/error-report.h"
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#include "qemu/main-loop.h"
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#include "mmu-book3s-v3.h"
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#include "hw/ppc/ppc.h"
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#include "helper_regs.h"
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/*****************************************************************************/
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/* SPR accesses */
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void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
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{
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qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
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env->spr[sprn]);
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}
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void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
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{
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qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
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env->spr[sprn]);
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}
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void helper_spr_core_write_generic(CPUPPCState *env, uint32_t sprn,
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target_ulong val)
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{
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CPUState *cs = env_cpu(env);
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CPUState *ccs;
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uint32_t nr_threads = cs->nr_threads;
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if (nr_threads == 1) {
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env->spr[sprn] = val;
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return;
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}
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THREAD_SIBLING_FOREACH(cs, ccs) {
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CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;
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cenv->spr[sprn] = val;
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}
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}
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void helper_spr_write_CTRL(CPUPPCState *env, uint32_t sprn,
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target_ulong val)
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{
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CPUState *cs = env_cpu(env);
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CPUState *ccs;
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uint32_t run = val & 1;
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uint32_t ts, ts_mask;
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assert(sprn == SPR_CTRL);
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env->spr[sprn] &= ~1U;
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env->spr[sprn] |= run;
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ts_mask = ~(1U << (8 + env->spr[SPR_TIR]));
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ts = run << (8 + env->spr[SPR_TIR]);
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THREAD_SIBLING_FOREACH(cs, ccs) {
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CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;
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cenv->spr[sprn] &= ts_mask;
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cenv->spr[sprn] |= ts;
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}
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}
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#ifdef TARGET_PPC64
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static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit,
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const char *caller, uint32_t cause,
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uintptr_t raddr)
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{
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qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n",
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bit, caller);
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env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
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raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr);
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}
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static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
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uint32_t sprn, uint32_t cause,
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uintptr_t raddr)
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{
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qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
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env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
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cause &= FSCR_IC_MASK;
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env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
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raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
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}
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#endif
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void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
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const char *caller, uint32_t cause)
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{
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#ifdef TARGET_PPC64
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if ((env->msr_mask & MSR_HVB) && !FIELD_EX64(env->msr, MSR, HV) &&
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!(env->spr[SPR_HFSCR] & (1UL << bit))) {
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raise_hv_fu_exception(env, bit, caller, cause, GETPC());
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}
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#endif
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}
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void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
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uint32_t sprn, uint32_t cause)
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{
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#ifdef TARGET_PPC64
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if (env->spr[SPR_FSCR] & (1ULL << bit)) {
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/* Facility is enabled, continue */
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return;
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}
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raise_fu_exception(env, bit, sprn, cause, GETPC());
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#endif
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}
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void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
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uint32_t sprn, uint32_t cause)
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{
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#ifdef TARGET_PPC64
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if (env->msr & (1ULL << bit)) {
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/* Facility is enabled, continue */
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return;
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}
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raise_fu_exception(env, bit, sprn, cause, GETPC());
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#endif
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}
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#if !defined(CONFIG_USER_ONLY)
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#ifdef TARGET_PPC64
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static void helper_mmcr0_facility_check(CPUPPCState *env, uint32_t bit,
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uint32_t sprn, uint32_t cause)
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{
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if (FIELD_EX64(env->msr, MSR, PR) &&
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!(env->spr[SPR_POWER_MMCR0] & (1ULL << bit))) {
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raise_fu_exception(env, bit, sprn, cause, GETPC());
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}
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}
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#endif
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void helper_store_sdr1(CPUPPCState *env, target_ulong val)
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{
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if (env->spr[SPR_SDR1] != val) {
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ppc_store_sdr1(env, val);
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tlb_flush(env_cpu(env));
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}
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}
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#if defined(TARGET_PPC64)
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void helper_store_ptcr(CPUPPCState *env, target_ulong val)
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{
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if (env->spr[SPR_PTCR] != val) {
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CPUState *cs = env_cpu(env);
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PowerPCCPU *cpu = env_archcpu(env);
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target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
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target_ulong patbsize = val & PTCR_PATS;
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qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, val);
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assert(!cpu->vhyp);
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assert(env->mmu_model & POWERPC_MMU_3_00);
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if (val & ~ptcr_mask) {
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error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
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val & ~ptcr_mask);
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val &= ptcr_mask;
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}
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if (patbsize > 24) {
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error_report("Invalid Partition Table size 0x" TARGET_FMT_lx
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" stored in PTCR", patbsize);
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return;
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}
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if (cs->nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
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env->spr[SPR_PTCR] = val;
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tlb_flush(cs);
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} else {
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CPUState *ccs;
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THREAD_SIBLING_FOREACH(cs, ccs) {
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PowerPCCPU *ccpu = POWERPC_CPU(ccs);
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CPUPPCState *cenv = &ccpu->env;
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cenv->spr[SPR_PTCR] = val;
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tlb_flush(ccs);
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}
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}
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}
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}
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void helper_store_pcr(CPUPPCState *env, target_ulong value)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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env->spr[SPR_PCR] = value & pcc->pcr_mask;
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}
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void helper_store_ciabr(CPUPPCState *env, target_ulong value)
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{
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ppc_store_ciabr(env, value);
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}
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void helper_store_dawr0(CPUPPCState *env, target_ulong value)
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{
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ppc_store_dawr0(env, value);
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}
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void helper_store_dawrx0(CPUPPCState *env, target_ulong value)
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{
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ppc_store_dawrx0(env, value);
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}
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/*
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* DPDES register is shared. Each bit reflects the state of the
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* doorbell interrupt of a thread of the same core.
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*/
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target_ulong helper_load_dpdes(CPUPPCState *env)
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{
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CPUState *cs = env_cpu(env);
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CPUState *ccs;
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uint32_t nr_threads = cs->nr_threads;
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target_ulong dpdes = 0;
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helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP);
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if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
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nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */
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}
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if (nr_threads == 1) {
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if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
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dpdes = 1;
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}
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return dpdes;
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}
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bql_lock();
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THREAD_SIBLING_FOREACH(cs, ccs) {
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PowerPCCPU *ccpu = POWERPC_CPU(ccs);
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CPUPPCState *cenv = &ccpu->env;
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uint32_t thread_id = ppc_cpu_tir(ccpu);
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if (cenv->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
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dpdes |= (0x1 << thread_id);
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}
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}
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bql_unlock();
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return dpdes;
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}
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void helper_store_dpdes(CPUPPCState *env, target_ulong val)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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CPUState *cs = env_cpu(env);
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CPUState *ccs;
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uint32_t nr_threads = cs->nr_threads;
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helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP);
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if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
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nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */
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}
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if (val & ~(nr_threads - 1)) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "
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TARGET_FMT_lx"\n", val);
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val &= (nr_threads - 1); /* Ignore the invalid bits */
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}
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if (nr_threads == 1) {
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ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1);
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return;
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}
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/* Does iothread need to be locked for walking CPU list? */
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bql_lock();
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THREAD_SIBLING_FOREACH(cs, ccs) {
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PowerPCCPU *ccpu = POWERPC_CPU(ccs);
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uint32_t thread_id = ppc_cpu_tir(ccpu);
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ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & (0x1 << thread_id));
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}
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bql_unlock();
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}
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/*
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* qemu-user breaks with pnv headers, so they go under ifdefs for now.
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* A clean up may be to move powernv specific registers and helpers into
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* target/ppc/pnv_helper.c
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*/
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#include "hw/ppc/pnv_core.h"
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/* Indirect SCOM (SPRC/SPRD) access to SCRATCH0-7 are implemented. */
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void helper_store_sprc(CPUPPCState *env, target_ulong val)
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{
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if (val & ~0x3f8ULL) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid SPRC register value "
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TARGET_FMT_lx"\n", val);
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return;
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}
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env->spr[SPR_POWER_SPRC] = val;
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}
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target_ulong helper_load_sprd(CPUPPCState *env)
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{
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/*
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* SPRD is a HV-only register for Power CPUs, so this will only be
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* accessed by powernv machines.
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*/
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PowerPCCPU *cpu = env_archcpu(env);
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PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
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target_ulong sprc = env->spr[SPR_POWER_SPRC];
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switch (sprc & 0x3e0) {
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case 0: /* SCRATCH0-3 */
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case 1: /* SCRATCH4-7 */
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return pc->scratch[(sprc >> 3) & 0x7];
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default:
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qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x"
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TARGET_FMT_lx"\n", sprc);
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break;
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}
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return 0;
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}
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void helper_store_sprd(CPUPPCState *env, target_ulong val)
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{
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target_ulong sprc = env->spr[SPR_POWER_SPRC];
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PowerPCCPU *cpu = env_archcpu(env);
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PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
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int nr;
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switch (sprc & 0x3e0) {
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case 0: /* SCRATCH0-3 */
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case 1: /* SCRATCH4-7 */
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/*
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* Log stores to SCRATCH, because some firmware uses these for
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* debugging and logging, but they would normally be read by the BMC,
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* which is not implemented in QEMU yet. This gives a way to get at the
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* information. Could also dump these upon checkstop.
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*/
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nr = (sprc >> 3) & 0x7;
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qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr);
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pc->scratch[nr] = val;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "mtSPRD: Unimplemented SPRC:0x"
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TARGET_FMT_lx"\n", sprc);
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break;
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}
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}
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#endif /* defined(TARGET_PPC64) */
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void helper_store_pidr(CPUPPCState *env, target_ulong val)
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{
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env->spr[SPR_BOOKS_PID] = (uint32_t)val;
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tlb_flush(env_cpu(env));
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}
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void helper_store_lpidr(CPUPPCState *env, target_ulong val)
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{
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env->spr[SPR_LPIDR] = (uint32_t)val;
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/*
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* We need to flush the TLB on LPID changes as we only tag HV vs
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* guest in TCG TLB. Also the quadrants means the HV will
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* potentially access and cache entries for the current LPID as
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* well.
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*/
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tlb_flush(env_cpu(env));
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}
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void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
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{
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/* Bits 26 & 27 affect single-stepping. */
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hreg_compute_hflags(env);
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/* Bits 28 & 29 affect reset or shutdown. */
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store_40x_dbcr0(env, val);
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}
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void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
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{
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store_40x_sler(env, val);
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}
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#endif
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/*****************************************************************************/
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/* Special registers manipulation */
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/*
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* This code is lifted from MacOnLinux. It is called whenever THRM1,2
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* or 3 is read an fixes up the values in such a way that will make
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* MacOS not hang. These registers exist on some 75x and 74xx
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* processors.
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*/
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void helper_fixup_thrm(CPUPPCState *env)
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{
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target_ulong v, t;
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int i;
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#define THRM1_TIN (1 << 31)
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#define THRM1_TIV (1 << 30)
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#define THRM1_THRES(x) (((x) & 0x7f) << 23)
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#define THRM1_TID (1 << 2)
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#define THRM1_TIE (1 << 1)
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#define THRM1_V (1 << 0)
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#define THRM3_E (1 << 0)
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if (!(env->spr[SPR_THRM3] & THRM3_E)) {
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return;
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}
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/* Note: Thermal interrupts are unimplemented */
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for (i = SPR_THRM1; i <= SPR_THRM2; i++) {
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v = env->spr[i];
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if (!(v & THRM1_V)) {
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continue;
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}
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v |= THRM1_TIV;
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v &= ~THRM1_TIN;
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t = v & THRM1_THRES(127);
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if ((v & THRM1_TID) && t < THRM1_THRES(24)) {
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v |= THRM1_TIN;
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}
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if (!(v & THRM1_TID) && t > THRM1_THRES(24)) {
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v |= THRM1_TIN;
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}
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env->spr[i] = v;
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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#if defined(TARGET_PPC64)
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void helper_clrbhrb(CPUPPCState *env)
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{
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helper_hfscr_facility_check(env, HFSCR_BHRB, "clrbhrb", FSCR_IC_BHRB);
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helper_mmcr0_facility_check(env, MMCR0_BHRBA_NR, 0, FSCR_IC_BHRB);
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if (env->flags & POWERPC_FLAG_BHRB) {
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memset(env->bhrb, 0, sizeof(env->bhrb));
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}
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}
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uint64_t helper_mfbhrbe(CPUPPCState *env, uint32_t bhrbe)
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{
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unsigned int index;
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helper_hfscr_facility_check(env, HFSCR_BHRB, "mfbhrbe", FSCR_IC_BHRB);
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helper_mmcr0_facility_check(env, MMCR0_BHRBA_NR, 0, FSCR_IC_BHRB);
|
|
|
|
if (!(env->flags & POWERPC_FLAG_BHRB) ||
|
|
(bhrbe >= env->bhrb_num_entries) ||
|
|
(env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE)) {
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Note: bhrb_offset is the byte offset for writing the
|
|
* next entry (over the oldest entry), which is why we
|
|
* must offset bhrbe by 1 to get to the 0th entry.
|
|
*/
|
|
index = ((env->bhrb_offset / sizeof(uint64_t)) - (bhrbe + 1)) %
|
|
env->bhrb_num_entries;
|
|
return env->bhrb[index];
|
|
}
|
|
#endif
|
|
#endif
|