57f5c1b093
The SH4 manual is not fully clear about that, but real hardware do not check for the PR bit, which allows to select between single or double precision, for the fabs instruction. This is probably what is meant by "Same operation is performed regardless of precision." Remove the check, and at the same time use a TCG instruction instead of a helper to clear one bit. LP: https://bugs.launchpad.net/qemu/+bug/1701821 Reported-by: Bruno Haible <bruno@clisp.org> Message-Id: <20170702202814.27793-2-aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
44 lines
1.9 KiB
C
44 lines
1.9 KiB
C
DEF_HELPER_1(ldtlb, void, env)
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DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
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DEF_HELPER_1(raise_slot_illegal_instruction, noreturn, env)
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DEF_HELPER_1(raise_fpu_disable, noreturn, env)
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DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env)
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DEF_HELPER_1(debug, noreturn, env)
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DEF_HELPER_1(sleep, noreturn, env)
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DEF_HELPER_2(trapa, noreturn, env, i32)
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DEF_HELPER_3(movcal, void, env, i32, i32)
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DEF_HELPER_1(discard_movcal_backup, void, env)
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DEF_HELPER_2(ocbi, void, env, i32)
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DEF_HELPER_3(macl, void, env, i32, i32)
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DEF_HELPER_3(macw, void, env, i32, i32)
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DEF_HELPER_2(ld_fpscr, void, env, i32)
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DEF_HELPER_FLAGS_3(fadd_FT, TCG_CALL_NO_WG, f32, env, f32, f32)
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DEF_HELPER_FLAGS_3(fadd_DT, TCG_CALL_NO_WG, f64, env, f64, f64)
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DEF_HELPER_FLAGS_2(fcnvsd_FT_DT, TCG_CALL_NO_WG, f64, env, f32)
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DEF_HELPER_FLAGS_2(fcnvds_DT_FT, TCG_CALL_NO_WG, f32, env, f64)
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DEF_HELPER_3(fcmp_eq_FT, void, env, f32, f32)
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DEF_HELPER_3(fcmp_eq_DT, void, env, f64, f64)
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DEF_HELPER_3(fcmp_gt_FT, void, env, f32, f32)
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DEF_HELPER_3(fcmp_gt_DT, void, env, f64, f64)
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DEF_HELPER_FLAGS_3(fdiv_FT, TCG_CALL_NO_WG, f32, env, f32, f32)
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DEF_HELPER_FLAGS_3(fdiv_DT, TCG_CALL_NO_WG, f64, env, f64, f64)
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DEF_HELPER_FLAGS_2(float_FT, TCG_CALL_NO_WG, f32, env, i32)
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DEF_HELPER_FLAGS_2(float_DT, TCG_CALL_NO_WG, f64, env, i32)
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DEF_HELPER_FLAGS_4(fmac_FT, TCG_CALL_NO_WG, f32, env, f32, f32, f32)
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DEF_HELPER_FLAGS_3(fmul_FT, TCG_CALL_NO_WG, f32, env, f32, f32)
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DEF_HELPER_FLAGS_3(fmul_DT, TCG_CALL_NO_WG, f64, env, f64, f64)
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DEF_HELPER_FLAGS_1(fneg_T, TCG_CALL_NO_RWG_SE, f32, f32)
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DEF_HELPER_FLAGS_3(fsub_FT, TCG_CALL_NO_WG, f32, env, f32, f32)
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DEF_HELPER_FLAGS_3(fsub_DT, TCG_CALL_NO_WG, f64, env, f64, f64)
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DEF_HELPER_FLAGS_2(fsqrt_FT, TCG_CALL_NO_WG, f32, env, f32)
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DEF_HELPER_FLAGS_2(fsqrt_DT, TCG_CALL_NO_WG, f64, env, f64)
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DEF_HELPER_FLAGS_2(ftrc_FT, TCG_CALL_NO_WG, i32, env, f32)
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DEF_HELPER_FLAGS_2(ftrc_DT, TCG_CALL_NO_WG, i32, env, f64)
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DEF_HELPER_3(fipr, void, env, i32, i32)
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DEF_HELPER_2(ftrv, void, env, i32)
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