fea4500841
Rather than relying on the X86XSaveArea structure definition, determine the offset of XSAVE state areas using CPUID leaf 0xd where possible (KVM and HVF). Signed-off-by: David Edmondson <david.edmondson@oracle.com> Message-Id: <20210705104632.2902400-8-david.edmondson@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
141 lines
3.8 KiB
C
141 lines
3.8 KiB
C
/*
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* i386 TCG cpu class initialization
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "helper-tcg.h"
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#include "qemu/accel.h"
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#include "hw/core/accel-cpu.h"
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#include "tcg-cpu.h"
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/* Frob eflags into and out of the CPU temporary format. */
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static void x86_cpu_exec_enter(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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env->df = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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}
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static void x86_cpu_exec_exit(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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env->eflags = cpu_compute_eflags(env);
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}
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static void x86_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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X86CPU *cpu = X86_CPU(cs);
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cpu->env.eip = tb->pc - tb->cs_base;
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}
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#include "hw/core/tcg-cpu-ops.h"
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static const struct TCGCPUOps x86_tcg_ops = {
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.initialize = tcg_x86_init,
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.synchronize_from_tb = x86_cpu_synchronize_from_tb,
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.cpu_exec_enter = x86_cpu_exec_enter,
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.cpu_exec_exit = x86_cpu_exec_exit,
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.cpu_exec_interrupt = x86_cpu_exec_interrupt,
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.do_interrupt = x86_cpu_do_interrupt,
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.tlb_fill = x86_cpu_tlb_fill,
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#ifndef CONFIG_USER_ONLY
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.debug_excp_handler = breakpoint_handler,
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#endif /* !CONFIG_USER_ONLY */
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};
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static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
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{
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/* for x86, all cpus use the same set of operations */
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cc->tcg_ops = &x86_tcg_ops;
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}
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static void tcg_cpu_class_init(CPUClass *cc)
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{
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cc->init_accel_cpu = tcg_cpu_init_ops;
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}
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static void tcg_cpu_xsave_init(void)
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{
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#define XO(bit, field) \
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x86_ext_save_areas[bit].offset = offsetof(X86XSaveArea, field);
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XO(XSTATE_FP_BIT, legacy);
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XO(XSTATE_SSE_BIT, legacy);
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XO(XSTATE_YMM_BIT, avx_state);
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XO(XSTATE_BNDREGS_BIT, bndreg_state);
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XO(XSTATE_BNDCSR_BIT, bndcsr_state);
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XO(XSTATE_OPMASK_BIT, opmask_state);
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XO(XSTATE_ZMM_Hi256_BIT, zmm_hi256_state);
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XO(XSTATE_Hi16_ZMM_BIT, hi16_zmm_state);
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XO(XSTATE_PKRU_BIT, pkru_state);
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#undef XO
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}
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/*
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* TCG-specific defaults that override all CPU models when using TCG
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*/
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static PropValue tcg_default_props[] = {
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{ "vme", "off" },
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{ NULL, NULL },
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};
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static void tcg_cpu_instance_init(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs);
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/* Special cases not set in the X86CPUDefinition structs: */
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x86_cpu_apply_props(cpu, tcg_default_props);
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tcg_cpu_xsave_init();
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}
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static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
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{
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AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
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#ifndef CONFIG_USER_ONLY
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acc->cpu_realizefn = tcg_cpu_realizefn;
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#endif /* CONFIG_USER_ONLY */
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acc->cpu_class_init = tcg_cpu_class_init;
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acc->cpu_instance_init = tcg_cpu_instance_init;
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}
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static const TypeInfo tcg_cpu_accel_type_info = {
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.name = ACCEL_CPU_NAME("tcg"),
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.parent = TYPE_ACCEL_CPU,
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.class_init = tcg_cpu_accel_class_init,
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.abstract = true,
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};
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static void tcg_cpu_accel_register_types(void)
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{
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type_register_static(&tcg_cpu_accel_type_info);
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}
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type_init(tcg_cpu_accel_register_types);
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