qemu/riscv at fe93582cf52ee67f6ab5a59051d354344010cfdc - qemu

History

sifive_u: Add clock DT node for GEM ethernet

The GEM ethernet on SiFive unleashed has fixed input clock
of 125MHz as-per SiFive FU540 manual. This patch updates FDT
generation for QEMU sifive_u machine to provide fixed-rate
clock for GEM ethernet.

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2018-12-20 12:03:12 -08:00

riscv_hart.h

…

riscv_htif.h

…

sifive_clint.h

…

sifive_e.h

hw/riscv/sifive_e: Create a SiFive E SoC object

2018-07-05 15:24:25 -07:00

sifive_plic.h

RISC-V: Use atomic_cmpxchg to update PLIC bitmaps