Fabiano Rosas fe4b5c4c33 target/ppc: 7xx: Set SRRs directly in exception code ...

The 7xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

2022-02-09 09:08:56 +01:00

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alpha

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arm

arm: force flag recalculation when messing with DAIF

2022-02-08 10:56:28 +00:00

avr

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cris

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hexagon

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hppa

hppa: Add support for an emulated TOC/NMI button.

2022-02-02 18:46:42 +01:00

i386

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m68k

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microblaze

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mips

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nios2

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openrisc

Remove unnecessary minimum_version_id_old fields

2022-01-28 15:38:23 +01:00

ppc

target/ppc: 7xx: Set SRRs directly in exception code

2022-02-09 09:08:56 +01:00

riscv

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rx

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s390x

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sh4

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sparc

Remove unnecessary minimum_version_id_old fields

2022-01-28 15:38:23 +01:00

tricore

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xtensa

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Kconfig

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meson.build

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