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Richard Henderson fe0a69cca5 target/hppa: Fix 32-bit operand masks for 0E FCVT 
We masked the wrong bits, which prevented some of the
32-bit R registers.  E.g. "fcnvxf,sgl,sgl fr22R,fr6R".

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 		2018-01-31 05:30:50 -08:00
..
alpha accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
arm -----BEGIN PGP SIGNATURE----- 2018-01-26 10:08:53 +00:00
cris accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
hppa target/hppa: Fix 32-bit operand masks for 0E FCVT 2018-01-31 05:30:50 -08:00
i386 accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
lm32 accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
m68k target/m68k: add HMP command "info tlb" 2018-01-25 16:02:25 +01:00
microblaze accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
mips accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
moxie accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
nios2 accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
openrisc accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
ppc target/ppc/kvm: Add cap_ppc_safe_[cache/bounds_check/indirect_branch] 2018-01-29 14:24:55 +11:00
s390x accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
sh4 accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
sparc accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
tilegx accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
tricore accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
unicore32 accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
xtensa accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00