qemu/include
Richard Henderson 2c3e83f92d Second RISC-V PR for QEMU 6.2
- ePMP CSR address updates
  - Convert internal interrupts to use QEMU GPIO lines
  - SiFive PWM support
  - Support for RISC-V ACLINT
  - SiFive PDMA fixes
  - Update to u-boot instructions for sifive_u
  - mstatus.SD bug fix for hypervisor extensions
  - OpenTitan fix for USB dev address
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Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-20210921' into staging

Second RISC-V PR for QEMU 6.2

 - ePMP CSR address updates
 - Convert internal interrupts to use QEMU GPIO lines
 - SiFive PWM support
 - Support for RISC-V ACLINT
 - SiFive PDMA fixes
 - Update to u-boot instructions for sifive_u
 - mstatus.SD bug fix for hypervisor extensions
 - OpenTitan fix for USB dev address

# gpg: Signature made Mon 20 Sep 2021 11:52:26 PM PDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair23/tags/pull-riscv-to-apply-20210921: (21 commits)
  hw/riscv: opentitan: Correct the USB Dev address
  target/riscv: csr: Rename HCOUNTEREN_CY and friends
  target/riscv: Backup/restore mstatus.SD bit when virtual register swapped
  docs/system/riscv: sifive_u: Update U-Boot instructions
  hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
  hw/dma: sifive_pdma: allow non-multiple transaction size transactions
  hw/dma: sifive_pdma: claim bit must be set before DMA transactions
  hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
  hw/riscv: virt: Add optional ACLINT support to virt machine
  hw/riscv: virt: Re-factor FDT generation
  hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
  hw/intc: Rename sifive_clint sources to riscv_aclint sources
  sifive_u: Connect the SiFive PWM device
  hw/timer: Add SiFive PWM support
  hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
  hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
  hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
  hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
  target/riscv: Expose interrupt pending bits as GPIO lines
  target/riscv: Fix satp write
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21 10:57:48 -07:00
..
authz
block block: Clarify that @bytes is no limit on *pnum 2021-09-15 15:54:07 +02:00
chardev chardev: add some comments about the class methods 2021-09-14 16:57:11 +04:00
crypto crypto: Make QCryptoTLSCreds* structures private 2021-06-29 18:30:24 +01:00
disas Drop the deprecated lm32 target 2021-05-12 18:20:25 +02:00
exec accel/tcg: Clear PAGE_WRITE before translation 2021-09-14 12:00:20 -07:00
fpu Remove leading underscores from QEMU defines 2021-06-21 05:49:01 +02:00
hw Second RISC-V PR for QEMU 6.2 2021-09-21 10:57:48 -07:00
io
libdecnumber
migration vfio: Support for RamDiscardManager in the vIOMMU case 2021-07-08 15:54:45 -04:00
monitor monitor: allow register hmp commands 2021-07-09 18:21:33 +02:00
net vhost_net: do not assume nvqs is always 2 2021-09-04 17:34:05 -04:00
qapi qapi: introduce forwarding visitor 2021-07-23 18:17:17 +02:00
qemu util/vfio-helpers: Pass Error handle to qemu_vfio_dma_map() 2021-09-07 09:08:24 +01:00
qom qom: export more functions for use with non-UserCreatable objects 2021-07-06 08:33:51 +02:00
scsi
semihosting
standard-headers linux-headers: Update 2021-07-09 11:01:06 +10:00
sysemu arm/hvf: Add a WFI handler 2021-09-21 16:28:26 +01:00
tcg tcg: Remove tcg_global_reg_new defines 2021-09-14 12:00:20 -07:00
ui ui/gtk-egl: Wait for the draw signal for dmabuf blobs 2021-09-15 08:41:59 +02:00
user Remove leading underscores from QEMU defines 2021-06-21 05:49:01 +02:00
elf.h linux-user: elf: s390x: Prepare for Vector enhancements facility 2021-06-21 08:48:21 +02:00
glib-compat.h configure: bump min required glib version to 2.56 2021-06-02 09:11:32 +02:00
qemu-common.h
qemu-io.h
trace-tcg.h