Frédéric Pétrot fc313c6434 exec/memop: Adding signedness to quad definitions ... Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-08 15:46:10 +10:00
..
trans_privileged.c.inc	target/riscv: Remove exit_tb and lookup_and_goto_ptr	2021-10-15 16:39:14 -07:00
trans_rva.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvb.c.inc	target/riscv: Use gen_shift*_per_ol for RVB, RVI	2021-10-22 23:35:47 +10:00
trans_rvd.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvf.c.inc	target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions	2021-10-28 14:39:23 +10:00
trans_rvh.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvi.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvm.c.inc	target/riscv: Use gen_arith_per_ol for RVM	2021-10-22 23:35:43 +10:00
trans_rvv.c.inc	target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns	2022-01-08 15:46:09 +10:00
trans_rvzfh.c.inc	target/riscv: zfh: implement zfhmin extension	2021-12-20 14:51:36 +10:00