qemu/include/hw/i2c
Cédric Le Goater 545d6bef70 aspeed/i2c: Add support for DMA transfers
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
transfers to and from DRAM.

A pair of registers defines the buffer address and the length of the
DMA transfer. The address should be aligned on 4 bytes and the maximum
length should not exceed 4K. The receive or transmit DMA transfer can
then be initiated with specific bits in the Command/Status register of
the controller.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-5-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-16 10:46:34 +00:00
..
aspeed_i2c.h aspeed/i2c: Add support for DMA transfers 2019-12-16 10:46:34 +00:00
bitbang_i2c.h hw/i2c/bitbang_i2c: Use in-place rather than malloc'd bitbang_i2c_interface struct 2019-07-03 10:51:35 +02:00
i2c.h Include hw/qdev-properties.h less 2019-08-16 13:31:53 +02:00
imx_i2c.h
microbit_i2c.h
pm_smbus.h Include exec/memory.h slightly less 2019-08-16 13:31:52 +02:00
ppc4xx_i2c.h hw/i2c/bitbang_i2c: Use in-place rather than malloc'd bitbang_i2c_interface struct 2019-07-03 10:51:35 +02:00
smbus_eeprom.h Include exec/memory.h slightly less 2019-08-16 13:31:52 +02:00
smbus_master.h i2c: Split smbus into parts 2019-02-27 21:06:08 -06:00
smbus_slave.h i2c:smbus_slave: Add an SMBus vmstate structure 2019-02-27 21:06:08 -06:00