8b1d5b3c35
There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
287 lines
7.2 KiB
C
287 lines
7.2 KiB
C
/*
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* CRIS virtual CPU header
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*
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* Copyright (c) 2007 AXIS Communications AB
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* Written by Edgar E. Iglesias
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CRIS_CPU_H
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#define CRIS_CPU_H
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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#define EXCP_NMI 1
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#define EXCP_GURU 2
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#define EXCP_BUSFAULT 3
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#define EXCP_IRQ 4
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#define EXCP_BREAK 5
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/* CRIS-specific interrupt pending bits. */
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#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
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/* CRUS CPU device objects interrupt lines. */
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/* PIC passes the vector for the IRQ as the value of it sends over qemu_irq */
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#define CRIS_CPU_IRQ 0
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#define CRIS_CPU_NMI 1
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/* Register aliases. R0 - R15 */
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#define R_FP 8
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#define R_SP 14
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#define R_ACR 15
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/* Support regs, P0 - P15 */
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#define PR_BZ 0
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#define PR_VR 1
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#define PR_PID 2
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#define PR_SRS 3
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#define PR_WZ 4
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#define PR_EXS 5
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#define PR_EDA 6
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#define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
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#define PR_MOF 7
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#define PR_DZ 8
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#define PR_EBP 9
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#define PR_ERP 10
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#define PR_SRP 11
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#define PR_NRP 12
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#define PR_CCS 13
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#define PR_USP 14
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#define PRV10_BRP 14
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#define PR_SPC 15
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/* CPU flags. */
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#define Q_FLAG 0x80000000
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#define M_FLAG_V32 0x40000000
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#define PFIX_FLAG 0x800 /* CRISv10 Only. */
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#define F_FLAG_V10 0x400
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#define P_FLAG_V10 0x200
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#define S_FLAG 0x200
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#define R_FLAG 0x100
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#define P_FLAG 0x80
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#define M_FLAG_V10 0x80
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#define U_FLAG 0x40
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#define I_FLAG 0x20
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#define X_FLAG 0x10
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#define N_FLAG 0x08
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#define Z_FLAG 0x04
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#define V_FLAG 0x02
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#define C_FLAG 0x01
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#define ALU_FLAGS 0x1F
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/* Condition codes. */
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#define CC_CC 0
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#define CC_CS 1
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#define CC_NE 2
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#define CC_EQ 3
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#define CC_VC 4
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#define CC_VS 5
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#define CC_PL 6
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#define CC_MI 7
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#define CC_LS 8
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#define CC_HI 9
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#define CC_GE 10
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#define CC_LT 11
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#define CC_GT 12
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#define CC_LE 13
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#define CC_A 14
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#define CC_P 15
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typedef struct {
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uint32_t hi;
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uint32_t lo;
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} TLBSet;
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typedef struct CPUCRISState {
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uint32_t regs[16];
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/* P0 - P15 are referred to as special registers in the docs. */
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uint32_t pregs[16];
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/* Pseudo register for the PC. Not directly accessible on CRIS. */
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uint32_t pc;
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/* Pseudo register for the kernel stack. */
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uint32_t ksp;
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/* Branch. */
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int dslot;
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int btaken;
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uint32_t btarget;
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/* Condition flag tracking. */
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uint32_t cc_op;
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uint32_t cc_mask;
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uint32_t cc_dest;
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uint32_t cc_src;
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uint32_t cc_result;
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/* size of the operation, 1 = byte, 2 = word, 4 = dword. */
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int cc_size;
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/* X flag at the time of cc snapshot. */
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int cc_x;
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/* CRIS has certain insns that lockout interrupts. */
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int locked_irq;
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int interrupt_vector;
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int fault_vector;
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int trap_vector;
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/* FIXME: add a check in the translator to avoid writing to support
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register sets beyond the 4th. The ISA allows up to 256! but in
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practice there is no core that implements more than 4.
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Support function registers are used to control units close to the
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core. Accesses do not pass down the normal hierarchy.
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*/
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uint32_t sregs[4][16];
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/* Linear feedback shift reg in the mmu. Used to provide pseudo
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randomness for the 'hint' the mmu gives to sw for choosing valid
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sets on TLB refills. */
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uint32_t mmu_rand_lfsr;
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/*
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* We just store the stores to the tlbset here for later evaluation
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* when the hw needs access to them.
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*
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* One for I and another for D.
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*/
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TLBSet tlbsets[2][4][16];
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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/* Members from load_info on are preserved across resets. */
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void *load_info;
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} CPUCRISState;
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/**
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* CRISCPU:
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* @env: #CPUCRISState
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*
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* A CRIS CPU.
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*/
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struct CRISCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPUCRISState env;
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};
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#ifndef CONFIG_USER_ONLY
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extern const VMStateDescription vmstate_cris_cpu;
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void cris_cpu_do_interrupt(CPUState *cpu);
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void crisv10_cpu_do_interrupt(CPUState *cpu);
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bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
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#endif
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void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
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hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void cris_initialize_tcg(void);
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void cris_initialize_crisv10_tcg(void);
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/* Instead of computing the condition codes after each CRIS instruction,
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* QEMU just stores one operand (called CC_SRC), the result
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* (called CC_DEST) and the type of operation (called CC_OP). When the
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* condition codes are needed, the condition codes can be calculated
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* using this information. Condition codes are not generated if they
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* are only needed for conditional branches.
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*/
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enum {
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CC_OP_DYNAMIC, /* Use env->cc_op */
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CC_OP_FLAGS,
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CC_OP_CMP,
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CC_OP_MOVE,
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CC_OP_ADD,
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CC_OP_ADDC,
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CC_OP_MCP,
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CC_OP_ADDU,
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CC_OP_SUB,
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CC_OP_SUBU,
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CC_OP_NEG,
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CC_OP_BTST,
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CC_OP_MULS,
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CC_OP_MULU,
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CC_OP_DSTEP,
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CC_OP_MSTEP,
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CC_OP_BOUND,
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CC_OP_OR,
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CC_OP_AND,
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CC_OP_XOR,
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CC_OP_LSL,
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CC_OP_LSR,
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CC_OP_ASR,
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CC_OP_LZ
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};
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/* CRIS uses 8k pages. */
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#define MMAP_SHIFT TARGET_PAGE_BITS
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#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
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#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
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/* MMU modes definitions */
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
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{
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return !!(env->pregs[PR_CCS] & U_FLAG);
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}
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bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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/* Support function regs. */
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#define SFR_RW_GC_CFG 0][0
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#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
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#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
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#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
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#define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
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#define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
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#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
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#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
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typedef CPUCRISState CPUArchState;
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typedef CRISCPU ArchCPU;
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#include "exec/cpu-all.h"
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static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = env->dslot |
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(env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
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| X_FLAG | PFIX_FLAG));
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}
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#define cpu_list cris_cpu_list
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void cris_cpu_list(void);
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#endif
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