9e4aa1fafe
This implements the Xilinx Versal eFuse, an one-time field-programmable non-volatile storage device. There is only one such device in the Xilinx Versal product family. This device has two separate mmio interfaces, a controller and a flatten readback. The controller provides interfaces for field-programming, configuration, control, and status. The flatten readback is a cache to provide a byte-accessible read-only interface to efficiently read efuse array. Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Signed-off-by: Tong Ho <tong.ho@xilinx.com> Message-id: 20210917052400.1249094-3-tong.ho@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
69 lines
2.3 KiB
C
69 lines
2.3 KiB
C
/*
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* Copyright (c) 2020 Xilinx Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef XLNX_VERSAL_EFUSE_H
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#define XLNX_VERSAL_EFUSE_H
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "hw/nvram/xlnx-efuse.h"
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#define XLNX_VERSAL_EFUSE_CTRL_R_MAX ((0x100 / 4) + 1)
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#define TYPE_XLNX_VERSAL_EFUSE_CTRL "xlnx,versal-efuse"
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#define TYPE_XLNX_VERSAL_EFUSE_CACHE "xlnx,pmc-efuse-cache"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCtrl, XLNX_VERSAL_EFUSE_CTRL);
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCache, XLNX_VERSAL_EFUSE_CACHE);
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struct XlnxVersalEFuseCtrl {
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SysBusDevice parent_obj;
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qemu_irq irq_efuse_imr;
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XlnxEFuse *efuse;
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void *extra_pg0_lock_spec; /* Opaque property */
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uint32_t extra_pg0_lock_n16;
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uint32_t regs[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
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RegisterInfo regs_info[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
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};
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struct XlnxVersalEFuseCache {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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XlnxEFuse *efuse;
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};
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/**
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* xlnx_versal_efuse_read_row:
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* @s: the efuse object
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* @bit: the bit-address within the 32-bit row to be read
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* @denied: if non-NULL, to receive true if the row is write-only
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*
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* Returns: the 32-bit word containing address @bit; 0 if @denies is true
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*/
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uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *s, uint32_t bit, bool *denied);
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#endif
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