qemu/target/riscv
Michael Clark fb73883964
RISC-V: Use riscv prefix consistently on cpu helpers
* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
  and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mode to riscv_cpu_set_mode

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11 15:56:21 -08:00
..
cpu_bits.h RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
cpu_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
cpu_user.h RISC-V Linux User Emulation 2018-03-07 08:30:28 +13:00
cpu.c RISC-V: Implement existential predicates for CSRs 2019-01-09 10:00:56 -08:00
cpu.h RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
csr.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
fpu_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
gdbstub.c RISC-V: Implement modular CSR helper interface 2019-01-08 13:59:09 -08:00
helper.h RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
Makefile.objs RISC-V: Implement modular CSR helper interface 2019-01-08 13:59:09 -08:00
op_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
pmp.c target/riscv/pmp.c: Fix pmp_decode_napot() 2018-12-20 12:26:39 -08:00
pmp.h RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
translate.c RISC-V: Mark mstatus.fs dirty 2019-02-11 15:56:21 -08:00