362 lines
13 KiB
C
362 lines
13 KiB
C
/*
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* Simple LatticeMico32 disassembler.
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*
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* Copyright (c) 2012 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <stdio.h>
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#include "disas/bfd.h"
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typedef enum {
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LM32_OP_SRUI = 0, LM32_OP_NORI, LM32_OP_MULI, LM32_OP_SH, LM32_OP_LB,
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LM32_OP_SRI, LM32_OP_XORI, LM32_OP_LH, LM32_OP_ANDI, LM32_OP_XNORI,
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LM32_OP_LW, LM32_OP_LHU, LM32_OP_SB, LM32_OP_ADDI, LM32_OP_ORI,
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LM32_OP_SLI, LM32_OP_LBU, LM32_OP_BE, LM32_OP_BG, LM32_OP_BGE,
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LM32_OP_BGEU, LM32_OP_BGU, LM32_OP_SW, LM32_OP_BNE, LM32_OP_ANDHI,
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LM32_OP_CMPEI, LM32_OP_CMPGI, LM32_OP_CMPGEI, LM32_OP_CMPGEUI,
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LM32_OP_CMPGUI, LM32_OP_ORHI, LM32_OP_CMPNEI, LM32_OP_SRU, LM32_OP_NOR,
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LM32_OP_MUL, LM32_OP_DIVU, LM32_OP_RCSR, LM32_OP_SR, LM32_OP_XOR,
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LM32_OP_ILL0, LM32_OP_AND, LM32_OP_XNOR, LM32_OP_ILL1, LM32_OP_SCALL,
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LM32_OP_SEXTB, LM32_OP_ADD, LM32_OP_OR, LM32_OP_SL, LM32_OP_B,
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LM32_OP_MODU, LM32_OP_SUB, LM32_OP_ILL2, LM32_OP_WCSR, LM32_OP_ILL3,
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LM32_OP_CALL, LM32_OP_SEXTH, LM32_OP_BI, LM32_OP_CMPE, LM32_OP_CMPG,
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LM32_OP_CMPGE, LM32_OP_CMPGEU, LM32_OP_CMPGU, LM32_OP_CALLI, LM32_OP_CMPNE,
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} Lm32Opcode;
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typedef enum {
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FMT_INVALID = 0, FMT_RRI5, FMT_RRI16, FMT_IMM26, FMT_LOAD, FMT_STORE,
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FMT_RRR, FMT_R, FMT_RNR, FMT_CRN, FMT_CNR, FMT_BREAK,
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} Lm32OpcodeFmt;
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typedef enum {
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LM32_CSR_IE = 0, LM32_CSR_IM, LM32_CSR_IP, LM32_CSR_ICC, LM32_CSR_DCC,
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LM32_CSR_CC, LM32_CSR_CFG, LM32_CSR_EBA, LM32_CSR_DC, LM32_CSR_DEBA,
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LM32_CSR_CFG2, LM32_CSR_JTX = 0xe, LM32_CSR_JRX, LM32_CSR_BP0,
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LM32_CSR_BP1, LM32_CSR_BP2, LM32_CSR_BP3, LM32_CSR_WP0 = 0x18,
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LM32_CSR_WP1, LM32_CSR_WP2, LM32_CSR_WP3,
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} Lm32CsrNum;
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typedef struct {
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int csr;
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const char *name;
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} Lm32CsrInfo;
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static const Lm32CsrInfo lm32_csr_info[] = {
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{LM32_CSR_IE, "ie", },
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{LM32_CSR_IM, "im", },
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{LM32_CSR_IP, "ip", },
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{LM32_CSR_ICC, "icc", },
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{LM32_CSR_DCC, "dcc", },
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{LM32_CSR_CC, "cc", },
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{LM32_CSR_CFG, "cfg", },
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{LM32_CSR_EBA, "eba", },
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{LM32_CSR_DC, "dc", },
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{LM32_CSR_DEBA, "deba", },
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{LM32_CSR_CFG2, "cfg2", },
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{LM32_CSR_JTX, "jtx", },
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{LM32_CSR_JRX, "jrx", },
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{LM32_CSR_BP0, "bp0", },
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{LM32_CSR_BP1, "bp1", },
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{LM32_CSR_BP2, "bp2", },
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{LM32_CSR_BP3, "bp3", },
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{LM32_CSR_WP0, "wp0", },
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{LM32_CSR_WP1, "wp1", },
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{LM32_CSR_WP2, "wp2", },
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{LM32_CSR_WP3, "wp3", },
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};
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static const Lm32CsrInfo *find_csr_info(int csr)
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{
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const Lm32CsrInfo *info;
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int i;
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for (i = 0; i < ARRAY_SIZE(lm32_csr_info); i++) {
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info = &lm32_csr_info[i];
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if (csr == info->csr) {
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return info;
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}
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}
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return NULL;
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}
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typedef struct {
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int reg;
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const char *name;
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} Lm32RegInfo;
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typedef enum {
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LM32_REG_R0 = 0, LM32_REG_R1, LM32_REG_R2, LM32_REG_R3, LM32_REG_R4,
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LM32_REG_R5, LM32_REG_R6, LM32_REG_R7, LM32_REG_R8, LM32_REG_R9,
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LM32_REG_R10, LM32_REG_R11, LM32_REG_R12, LM32_REG_R13, LM32_REG_R14,
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LM32_REG_R15, LM32_REG_R16, LM32_REG_R17, LM32_REG_R18, LM32_REG_R19,
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LM32_REG_R20, LM32_REG_R21, LM32_REG_R22, LM32_REG_R23, LM32_REG_R24,
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LM32_REG_R25, LM32_REG_GP, LM32_REG_FP, LM32_REG_SP, LM32_REG_RA,
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LM32_REG_EA, LM32_REG_BA,
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} Lm32RegNum;
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static const Lm32RegInfo lm32_reg_info[] = {
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{LM32_REG_R0, "r0", },
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{LM32_REG_R1, "r1", },
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{LM32_REG_R2, "r2", },
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{LM32_REG_R3, "r3", },
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{LM32_REG_R4, "r4", },
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{LM32_REG_R5, "r5", },
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{LM32_REG_R6, "r6", },
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{LM32_REG_R7, "r7", },
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{LM32_REG_R8, "r8", },
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{LM32_REG_R9, "r9", },
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{LM32_REG_R10, "r10", },
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{LM32_REG_R11, "r11", },
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{LM32_REG_R12, "r12", },
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{LM32_REG_R13, "r13", },
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{LM32_REG_R14, "r14", },
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{LM32_REG_R15, "r15", },
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{LM32_REG_R16, "r16", },
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{LM32_REG_R17, "r17", },
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{LM32_REG_R18, "r18", },
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{LM32_REG_R19, "r19", },
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{LM32_REG_R20, "r20", },
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{LM32_REG_R21, "r21", },
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{LM32_REG_R22, "r22", },
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{LM32_REG_R23, "r23", },
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{LM32_REG_R24, "r24", },
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{LM32_REG_R25, "r25", },
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{LM32_REG_GP, "gp", },
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{LM32_REG_FP, "fp", },
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{LM32_REG_SP, "sp", },
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{LM32_REG_RA, "ra", },
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{LM32_REG_EA, "ea", },
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{LM32_REG_BA, "ba", },
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};
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static const Lm32RegInfo *find_reg_info(int reg)
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{
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assert(ARRAY_SIZE(lm32_reg_info) == 32);
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return &lm32_reg_info[reg & 0x1f];
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}
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typedef struct {
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struct {
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uint32_t code;
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uint32_t mask;
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} op;
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const char *name;
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const char *args_fmt;
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} Lm32OpcodeInfo;
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static const Lm32OpcodeInfo lm32_opcode_info[] = {
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/* pseudo instructions */
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{{0x34000000, 0xffffffff}, "nop", NULL},
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{{0xac000002, 0xffffffff}, "break", NULL},
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{{0xac000003, 0xffffffff}, "scall", NULL},
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{{0xc3e00000, 0xffffffff}, "bret", NULL},
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{{0xc3c00000, 0xffffffff}, "eret", NULL},
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{{0xc3a00000, 0xffffffff}, "ret", NULL},
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{{0xa4000000, 0xfc1f07ff}, "not", "%2, %0"},
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{{0xb8000000, 0xfc1f07ff}, "mv", "%2, %0"},
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{{0x71e00000, 0xffe00000}, "mvhi", "%1, %u"},
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{{0x34000000, 0xffe00000}, "mvi", "%1, %s"},
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#define _O(op) {op << 26, 0x3f << 26}
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/* regular opcodes */
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{_O(LM32_OP_ADD), "add", "%2, %0, %1" },
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{_O(LM32_OP_ADDI), "addi", "%1, %0, %s" },
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{_O(LM32_OP_AND), "and", "%2, %0, %1" },
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{_O(LM32_OP_ANDHI), "andhi", "%1, %0, %u" },
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{_O(LM32_OP_ANDI), "andi", "%1, %0, %u" },
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{_O(LM32_OP_B), "b", "%0", },
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{_O(LM32_OP_BE), "be", "%1, %0, %r" },
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{_O(LM32_OP_BG), "bg", "%1, %0, %r" },
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{_O(LM32_OP_BGE), "bge", "%1, %0, %r" },
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{_O(LM32_OP_BGEU), "bgeu", "%1, %0, %r" },
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{_O(LM32_OP_BGU), "bgu", "%1, %0, %r" },
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{_O(LM32_OP_BI), "bi", "%R", },
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{_O(LM32_OP_BNE), "bne", "%1, %0, %r" },
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{_O(LM32_OP_CALL), "call", "%0", },
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{_O(LM32_OP_CALLI), "calli", "%R", },
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{_O(LM32_OP_CMPE), "cmpe", "%2, %0, %1" },
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{_O(LM32_OP_CMPEI), "cmpei", "%1, %0, %s" },
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{_O(LM32_OP_CMPG), "cmpg", "%2, %0, %1" },
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{_O(LM32_OP_CMPGE), "cmpge", "%2, %0, %1" },
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{_O(LM32_OP_CMPGEI), "cmpgei", "%1, %0, %s" },
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{_O(LM32_OP_CMPGEU), "cmpgeu", "%2, %0, %1" },
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{_O(LM32_OP_CMPGEUI), "cmpgeui", "%1, %0, %s" },
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{_O(LM32_OP_CMPGI), "cmpgi", "%1, %0, %s" },
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{_O(LM32_OP_CMPGU), "cmpgu", "%2, %0, %1" },
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{_O(LM32_OP_CMPGUI), "cmpgui", "%1, %0, %s" },
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{_O(LM32_OP_CMPNE), "cmpne", "%2, %0, %1" },
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{_O(LM32_OP_CMPNEI), "cmpnei", "%1, %0, %s" },
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{_O(LM32_OP_DIVU), "divu", "%2, %0, %1" },
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{_O(LM32_OP_LB), "lb", "%1, (%0+%s)" },
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{_O(LM32_OP_LBU), "lbu", "%1, (%0+%s)" },
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{_O(LM32_OP_LH), "lh", "%1, (%0+%s)" },
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{_O(LM32_OP_LHU), "lhu", "%1, (%0+%s)" },
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{_O(LM32_OP_LW), "lw", "%1, (%0+%s)" },
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{_O(LM32_OP_MODU), "modu", "%2, %0, %1" },
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{_O(LM32_OP_MULI), "muli", "%1, %0, %s" },
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{_O(LM32_OP_MUL), "mul", "%2, %0, %1" },
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{_O(LM32_OP_NORI), "nori", "%1, %0, %u" },
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{_O(LM32_OP_NOR), "nor", "%2, %0, %1" },
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{_O(LM32_OP_ORHI), "orhi", "%1, %0, %u" },
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{_O(LM32_OP_ORI), "ori", "%1, %0, %u" },
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{_O(LM32_OP_OR), "or", "%2, %0, %1" },
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{_O(LM32_OP_RCSR), "rcsr", "%2, %c", },
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{_O(LM32_OP_SB), "sb", "(%0+%s), %1" },
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{_O(LM32_OP_SEXTB), "sextb", "%2, %0", },
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{_O(LM32_OP_SEXTH), "sexth", "%2, %0", },
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{_O(LM32_OP_SH), "sh", "(%0+%s), %1" },
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{_O(LM32_OP_SLI), "sli", "%1, %0, %h" },
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{_O(LM32_OP_SL), "sl", "%2, %0, %1" },
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{_O(LM32_OP_SRI), "sri", "%1, %0, %h" },
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{_O(LM32_OP_SR), "sr", "%2, %0, %1" },
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{_O(LM32_OP_SRUI), "srui", "%1, %0, %d" },
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{_O(LM32_OP_SRU), "sru", "%2, %0, %s" },
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{_O(LM32_OP_SUB), "sub", "%2, %0, %s" },
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{_O(LM32_OP_SW), "sw", "(%0+%s), %1" },
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{_O(LM32_OP_WCSR), "wcsr", "%c, %1", },
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{_O(LM32_OP_XNORI), "xnori", "%1, %0, %u" },
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{_O(LM32_OP_XNOR), "xnor", "%2, %0, %1" },
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{_O(LM32_OP_XORI), "xori", "%1, %0, %u" },
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{_O(LM32_OP_XOR), "xor", "%2, %0, %1" },
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#undef _O
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};
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static const Lm32OpcodeInfo *find_opcode_info(uint32_t opcode)
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{
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const Lm32OpcodeInfo *info;
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int i;
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for (i = 0; i < ARRAY_SIZE(lm32_opcode_info); i++) {
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info = &lm32_opcode_info[i];
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if ((opcode & info->op.mask) == info->op.code) {
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return info;
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}
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}
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return NULL;
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}
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int print_insn_lm32(bfd_vma memaddr, struct disassemble_info *info)
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{
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fprintf_function fprintf_fn = info->fprintf_func;
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void *stream = info->stream;
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int rc;
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uint8_t insn[4];
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const Lm32OpcodeInfo *opc_info;
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uint32_t op;
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const char *args_fmt;
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rc = info->read_memory_func(memaddr, insn, 4, info);
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if (rc != 0) {
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info->memory_error_func(rc, memaddr, info);
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return -1;
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}
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fprintf_fn(stream, "%02x %02x %02x %02x ",
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insn[0], insn[1], insn[2], insn[3]);
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op = bfd_getb32(insn);
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opc_info = find_opcode_info(op);
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if (opc_info) {
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fprintf_fn(stream, "%-8s ", opc_info->name);
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args_fmt = opc_info->args_fmt;
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while (args_fmt && *args_fmt) {
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if (*args_fmt == '%') {
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switch (*(++args_fmt)) {
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case '0': {
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uint8_t r0;
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const char *r0_name;
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r0 = (op >> 21) & 0x1f;
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r0_name = find_reg_info(r0)->name;
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fprintf_fn(stream, "%s", r0_name);
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break;
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}
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case '1': {
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uint8_t r1;
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const char *r1_name;
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r1 = (op >> 16) & 0x1f;
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r1_name = find_reg_info(r1)->name;
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fprintf_fn(stream, "%s", r1_name);
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break;
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}
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case '2': {
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uint8_t r2;
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const char *r2_name;
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r2 = (op >> 11) & 0x1f;
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r2_name = find_reg_info(r2)->name;
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fprintf_fn(stream, "%s", r2_name);
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break;
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}
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case 'c': {
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uint8_t csr;
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const char *csr_name;
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csr = (op >> 21) & 0x1f;
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csr_name = find_csr_info(csr)->name;
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if (csr_name) {
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fprintf_fn(stream, "%s", csr_name);
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} else {
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fprintf_fn(stream, "0x%x", csr);
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}
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break;
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}
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case 'u': {
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uint16_t u16;
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u16 = op & 0xffff;
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fprintf_fn(stream, "0x%x", u16);
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break;
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}
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case 's': {
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int16_t s16;
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s16 = (int16_t)(op & 0xffff);
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fprintf_fn(stream, "%d", s16);
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break;
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}
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case 'r': {
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uint32_t rela;
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rela = memaddr + (((int16_t)(op & 0xffff)) << 2);
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fprintf_fn(stream, "%x", rela);
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break;
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}
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case 'R': {
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uint32_t rela;
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int32_t imm26;
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imm26 = (int32_t)((op & 0x3ffffff) << 6) >> 4;
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rela = memaddr + imm26;
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fprintf_fn(stream, "%x", rela);
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break;
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}
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case 'h': {
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uint8_t u5;
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u5 = (op & 0x1f);
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fprintf_fn(stream, "%d", u5);
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break;
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}
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default:
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break;
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}
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} else {
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fprintf_fn(stream, "%c", *args_fmt);
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}
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args_fmt++;
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}
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} else {
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fprintf_fn(stream, ".word 0x%x", op);
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}
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return 4;
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}
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