f95d7cc7fe
BEHAVIOUR CHANGE The ppc hash mmu hashes each virtual address to a primary and secondary possible hash bucket (aka PTE group or PTEG) each with 8 PTEs. Then we need a linear search through the PTEs to find the correct one for the virtual address we're translating. It is a programming error for the guest to insert multiple PTEs mapping the same virtual address into a PTEG - in this case the ppc architecture says the MMU can either act as if just one was present, or give a machine check. Currently our code takes the first matching PTE in a PTEG if it finds a successful translation. But if a matching PTE is found, but permission bits don't allow the access, we keep looking through the PTEG, checking that any other matching PTEs contain an identical translation. That behaviour is perhaps not exactly wrong, but it's certainly not useful. This patch changes it to always just find the first matching PTE in a PTEG. In addition, if we get a permissions problem on the primary PTEG, we then search the secondary PTEG. This is incorrect - a permission denying PTE in the primary PTEG should not be overwritten by an access granting PTE in the secondary (although again, it would be a programming error for the guest to set up such a situation anyway). So additionally we update the code to only search the secondary PTEG if no matching PTE is found in the primary at all. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
586 lines
16 KiB
C
586 lines
16 KiB
C
/*
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* PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright (c) 2013 David Gibson, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "helper.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "mmu-hash64.h"
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//#define DEBUG_MMU
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//#define DEBUG_SLB
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#ifdef DEBUG_MMU
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# define LOG_MMU(...) qemu_log(__VA_ARGS__)
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# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
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#else
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# define LOG_MMU(...) do { } while (0)
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# define LOG_MMU_STATE(...) do { } while (0)
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#endif
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#ifdef DEBUG_SLB
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# define LOG_SLB(...) qemu_log(__VA_ARGS__)
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#else
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# define LOG_SLB(...) do { } while (0)
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#endif
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struct mmu_ctx_hash64 {
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hwaddr raddr; /* Real address */
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int prot; /* Protection bits */
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hwaddr hash[2]; /* Pagetable hash values */
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target_ulong ptem; /* Virtual segment ID | API */
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int key; /* Access key */
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};
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/*
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* SLB handling
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*/
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static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
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{
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uint64_t esid_256M, esid_1T;
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int n;
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LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
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esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
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esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
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for (n = 0; n < env->slb_nr; n++) {
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ppc_slb_t *slb = &env->slb[n];
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LOG_SLB("%s: slot %d %016" PRIx64 " %016"
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PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
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/* We check for 1T matches on all MMUs here - if the MMU
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* doesn't have 1T segment support, we will have prevented 1T
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* entries from being inserted in the slbmte code. */
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if (((slb->esid == esid_256M) &&
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((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
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|| ((slb->esid == esid_1T) &&
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((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
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return slb;
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}
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}
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return NULL;
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}
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void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
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{
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int i;
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uint64_t slbe, slbv;
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cpu_synchronize_state(env);
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cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
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for (i = 0; i < env->slb_nr; i++) {
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slbe = env->slb[i].esid;
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slbv = env->slb[i].vsid;
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if (slbe == 0 && slbv == 0) {
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continue;
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}
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cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
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i, slbe, slbv);
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}
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}
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void helper_slbia(CPUPPCState *env)
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{
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int n, do_invalidate;
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do_invalidate = 0;
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/* XXX: Warning: slbia never invalidates the first segment */
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for (n = 1; n < env->slb_nr; n++) {
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ppc_slb_t *slb = &env->slb[n];
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if (slb->esid & SLB_ESID_V) {
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slb->esid &= ~SLB_ESID_V;
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/* XXX: given the fact that segment size is 256 MB or 1TB,
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* and we still don't have a tlb_flush_mask(env, n, mask)
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* in QEMU, we just invalidate all TLBs
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*/
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do_invalidate = 1;
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}
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}
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if (do_invalidate) {
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tlb_flush(env, 1);
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}
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}
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void helper_slbie(CPUPPCState *env, target_ulong addr)
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{
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ppc_slb_t *slb;
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slb = slb_lookup(env, addr);
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if (!slb) {
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return;
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}
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if (slb->esid & SLB_ESID_V) {
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slb->esid &= ~SLB_ESID_V;
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/* XXX: given the fact that segment size is 256 MB or 1TB,
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* and we still don't have a tlb_flush_mask(env, n, mask)
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* in QEMU, we just invalidate all TLBs
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*/
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tlb_flush(env, 1);
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}
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}
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int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
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{
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int slot = rb & 0xfff;
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ppc_slb_t *slb = &env->slb[slot];
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if (rb & (0x1000 - env->slb_nr)) {
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return -1; /* Reserved bits set or slot too high */
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}
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if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
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return -1; /* Bad segment size */
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}
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if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
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return -1; /* 1T segment on MMU that doesn't support it */
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}
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/* Mask out the slot number as we store the entry */
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slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
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slb->vsid = rs;
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LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
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" %016" PRIx64 "\n", __func__, slot, rb, rs,
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slb->esid, slb->vsid);
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return 0;
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}
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static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
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target_ulong *rt)
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{
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int slot = rb & 0xfff;
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ppc_slb_t *slb = &env->slb[slot];
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if (slot >= env->slb_nr) {
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return -1;
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}
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*rt = slb->esid;
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return 0;
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}
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static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
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target_ulong *rt)
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{
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int slot = rb & 0xfff;
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ppc_slb_t *slb = &env->slb[slot];
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if (slot >= env->slb_nr) {
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return -1;
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}
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*rt = slb->vsid;
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return 0;
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}
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void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
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{
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if (ppc_store_slb(env, rb, rs) < 0) {
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helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL);
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}
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}
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target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
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{
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target_ulong rt = 0;
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if (ppc_load_slb_esid(env, rb, &rt) < 0) {
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helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL);
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}
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return rt;
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}
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target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
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{
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target_ulong rt = 0;
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if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
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helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL);
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}
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return rt;
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}
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/*
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* 64-bit hash table MMU handling
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*/
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static int ppc_hash64_pp_check(int key, int pp, bool nx)
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{
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int access;
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/* Compute access rights */
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/* When pp is 4, 5 or 7, the result is undefined. Set it to noaccess */
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access = 0;
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if (key == 0) {
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switch (pp) {
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case 0x0:
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case 0x1:
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case 0x2:
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access |= PAGE_WRITE;
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/* No break here */
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case 0x3:
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case 0x6:
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access |= PAGE_READ;
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break;
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}
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} else {
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switch (pp) {
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case 0x0:
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case 0x6:
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access = 0;
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break;
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case 0x1:
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case 0x3:
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access = PAGE_READ;
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break;
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case 0x2:
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access = PAGE_READ | PAGE_WRITE;
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break;
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}
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}
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if (!nx) {
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access |= PAGE_EXEC;
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}
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return access;
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}
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static int ppc_hash64_check_prot(int prot, int rwx)
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{
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int ret;
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if (rwx == 2) {
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if (prot & PAGE_EXEC) {
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ret = 0;
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} else {
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ret = -2;
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}
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} else if (rwx == 1) {
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if (prot & PAGE_WRITE) {
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ret = 0;
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} else {
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ret = -2;
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}
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} else {
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if (prot & PAGE_READ) {
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ret = 0;
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} else {
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ret = -2;
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}
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}
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return ret;
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}
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static bool pte64_match(target_ulong pte0, target_ulong pte1,
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bool secondary, target_ulong ptem)
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{
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return (pte0 & HPTE64_V_VALID)
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&& (secondary == !!(pte0 & HPTE64_V_SECONDARY))
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&& HPTE64_V_COMPARE(pte0, ptem);
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}
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static int pte64_check(struct mmu_ctx_hash64 *ctx, target_ulong pte0,
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target_ulong pte1, int rwx)
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{
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int access, ret, pp;
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bool nx;
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pp = (pte1 & HPTE64_R_PP) | ((pte1 & HPTE64_R_PP0) >> 61);
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/* No execute if either noexec or guarded bits set */
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nx = (pte1 & HPTE64_R_N) || (pte1 & HPTE64_R_G);
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/* Compute access rights */
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access = ppc_hash64_pp_check(ctx->key, pp, nx);
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/* Keep the matching PTE informations */
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ctx->raddr = pte1;
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ctx->prot = access;
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ret = ppc_hash64_check_prot(ctx->prot, rwx);
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if (ret == 0) {
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/* Access granted */
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LOG_MMU("PTE access granted !\n");
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} else {
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/* Access right violation */
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LOG_MMU("PTE access rejected\n");
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}
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return ret;
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}
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static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx,
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target_ulong *pte1p,
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int ret, int rw)
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{
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int store = 0;
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/* Update page flags */
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if (!(*pte1p & HPTE64_R_R)) {
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/* Update accessed flag */
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*pte1p |= HPTE64_R_R;
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store = 1;
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}
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if (!(*pte1p & HPTE64_R_C)) {
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if (rw == 1 && ret == 0) {
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/* Update changed flag */
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*pte1p |= HPTE64_R_C;
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store = 1;
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} else {
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/* Force page fault for first write access */
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ctx->prot &= ~PAGE_WRITE;
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}
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}
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return store;
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}
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/* PTE table lookup */
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static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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target_ulong eaddr, int h, int rwx, int target_page_bits)
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{
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hwaddr pteg_off;
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target_ulong pte0, pte1;
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int i, good = -1;
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int ret;
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ret = -1; /* No entry found */
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pteg_off = (ctx->hash[h] * HASH_PTEG_SIZE_64) & env->htab_mask;
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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pte0 = ppc_hash64_load_hpte0(env, pteg_off + i*HASH_PTE_SIZE_64);
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pte1 = ppc_hash64_load_hpte1(env, pteg_off + i*HASH_PTE_SIZE_64);
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LOG_MMU("Load pte from %016" HWADDR_PRIx " => " TARGET_FMT_lx " "
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TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
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pteg_off + (i * 16), pte0, pte1, !!(pte0 & HPTE64_V_VALID),
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h, !!(pte0 & HPTE64_V_SECONDARY), ctx->ptem);
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if (pte64_match(pte0, pte1, h, ctx->ptem)) {
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good = i;
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break;
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}
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}
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if (good != -1) {
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ret = pte64_check(ctx, pte0, pte1, rwx);
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LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n",
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ctx->raddr, ctx->prot, ret);
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/* Update page flags */
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pte1 = ctx->raddr;
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if (ppc_hash64_pte_update_flags(ctx, &pte1, ret, rwx) == 1) {
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ppc_hash64_store_hpte1(env, pteg_off + good * HASH_PTE_SIZE_64, pte1);
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}
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}
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/* We have a TLB that saves 4K pages, so let's
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* split a huge page to 4k chunks */
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if (target_page_bits != TARGET_PAGE_BITS) {
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ctx->raddr |= (eaddr & ((1 << target_page_bits) - 1))
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& TARGET_PAGE_MASK;
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}
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return ret;
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}
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static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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target_ulong eaddr, int rwx)
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{
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hwaddr hash;
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target_ulong vsid;
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int pr, target_page_bits;
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int ret, ret2;
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ppc_slb_t *slb;
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target_ulong pageaddr;
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int segment_bits;
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/* 1. Handle real mode accesses */
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if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
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/* Translation is off */
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/* In real mode the top 4 effective address bits are ignored */
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ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
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ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
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return 0;
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}
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/* 2. Translation is on, so look up the SLB */
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slb = slb_lookup(env, eaddr);
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if (!slb) {
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return -5;
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}
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/* 3. Check for segment level no-execute violation */
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if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
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return -3;
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}
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pr = msr_pr;
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if (slb->vsid & SLB_VSID_B) {
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vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
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segment_bits = 40;
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} else {
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vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
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segment_bits = 28;
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}
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target_page_bits = (slb->vsid & SLB_VSID_L)
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? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
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ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP)
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: (slb->vsid & SLB_VSID_KS));
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pageaddr = eaddr & ((1ULL << segment_bits)
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- (1ULL << target_page_bits));
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if (slb->vsid & SLB_VSID_B) {
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hash = vsid ^ (vsid << 25) ^ (pageaddr >> target_page_bits);
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} else {
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hash = vsid ^ (pageaddr >> target_page_bits);
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}
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/* Only 5 bits of the page index are used in the AVPN */
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ctx->ptem = (slb->vsid & SLB_VSID_PTEM) |
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((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));
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LOG_MMU("pte segment: key=%d nx %d vsid " TARGET_FMT_lx "\n",
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ctx->key, !!(slb->vsid & SLB_VSID_N), vsid);
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ret = -1;
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/* Page address translation */
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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ctx->hash[0] = hash;
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|
ctx->hash[1] = ~hash;
|
|
|
|
LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
|
|
" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
|
|
" hash=" TARGET_FMT_plx "\n",
|
|
env->htab_base, env->htab_mask, vsid, ctx->ptem,
|
|
ctx->hash[0]);
|
|
/* Primary table lookup */
|
|
ret = find_pte64(env, ctx, eaddr, 0, rwx, target_page_bits);
|
|
if (ret == -1) {
|
|
/* Secondary table lookup */
|
|
LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
|
|
" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
|
|
" hash=" TARGET_FMT_plx "\n", env->htab_base,
|
|
env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
|
|
ret2 = find_pte64(env, ctx, eaddr, 1, rwx, target_page_bits);
|
|
if (ret2 != -1) {
|
|
ret = ret2;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
|
|
{
|
|
struct mmu_ctx_hash64 ctx;
|
|
|
|
if (unlikely(ppc_hash64_translate(env, &ctx, addr, 0) != 0)) {
|
|
return -1;
|
|
}
|
|
|
|
return ctx.raddr & TARGET_PAGE_MASK;
|
|
}
|
|
|
|
int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx,
|
|
int mmu_idx)
|
|
{
|
|
struct mmu_ctx_hash64 ctx;
|
|
int ret = 0;
|
|
|
|
ret = ppc_hash64_translate(env, &ctx, address, rwx);
|
|
if (ret == 0) {
|
|
tlb_set_page(env, address & TARGET_PAGE_MASK,
|
|
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
|
|
mmu_idx, TARGET_PAGE_SIZE);
|
|
ret = 0;
|
|
} else if (ret < 0) {
|
|
LOG_MMU_STATE(env);
|
|
if (rwx == 2) {
|
|
switch (ret) {
|
|
case -1:
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x40000000;
|
|
break;
|
|
case -2:
|
|
/* Access rights violation */
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x08000000;
|
|
break;
|
|
case -3:
|
|
/* No execute protection violation */
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x10000000;
|
|
break;
|
|
case -5:
|
|
/* No match in segment table */
|
|
env->exception_index = POWERPC_EXCP_ISEG;
|
|
env->error_code = 0;
|
|
break;
|
|
}
|
|
} else {
|
|
switch (ret) {
|
|
case -1:
|
|
/* No matches in page tables or TLB */
|
|
env->exception_index = POWERPC_EXCP_DSI;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = address;
|
|
if (rwx == 1) {
|
|
env->spr[SPR_DSISR] = 0x42000000;
|
|
} else {
|
|
env->spr[SPR_DSISR] = 0x40000000;
|
|
}
|
|
break;
|
|
case -2:
|
|
/* Access rights violation */
|
|
env->exception_index = POWERPC_EXCP_DSI;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = address;
|
|
if (rwx == 1) {
|
|
env->spr[SPR_DSISR] = 0x0A000000;
|
|
} else {
|
|
env->spr[SPR_DSISR] = 0x08000000;
|
|
}
|
|
break;
|
|
case -5:
|
|
/* No match in segment table */
|
|
env->exception_index = POWERPC_EXCP_DSEG;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = address;
|
|
break;
|
|
}
|
|
}
|
|
#if 0
|
|
printf("%s: set exception to %d %02x\n", __func__,
|
|
env->exception, env->error_code);
|
|
#endif
|
|
ret = 1;
|
|
}
|
|
|
|
return ret;
|
|
}
|