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The more recent IBM power processors have an embedded I2C controller that is accessible by software via the XSCOM address space. Each instance of the I2C controller is capable of controlling multiple I2C buses (one at a time). Prior to beginning a transaction on an I2C bus, the bus must be selected by writing the port number associated with the bus into the PORT_NUM field of the MODE register. Once an I2C bus is selected, the status of the bus can be determined by reading the Status and Extended Status registers. I2C bus transactions can be started by writing a command to the Command register and reading/writing data from/to the FIFO register. Not supported : . 10 bit I2C addresses . Multimaster . Slave Signed-off-by: Cédric Le Goater <clg@kaod.org> [milesg: Split wiring to powernv9 into its own commit] [milesg: Added more detail to commit message] [milesg: Added SPDX Licensed Identifier to new files] [milesg: updated copyright dates] [milesg: Added use of g_autofree] [milesg: Added NULL check after pnv_i2c_get_bus] Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <20231016222013.3739530-2-milesg@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
39 lines
672 B
C
39 lines
672 B
C
/*
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* QEMU PowerPC PowerNV Processor I2C model
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*
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* Copyright (c) 2019-2023, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef PPC_PNV_I2C_H
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#define PPC_PNV_I2C_H
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#include "hw/ppc/pnv.h"
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#include "hw/i2c/i2c.h"
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#include "qemu/fifo8.h"
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#define TYPE_PNV_I2C "pnv-i2c"
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#define PNV_I2C(obj) OBJECT_CHECK(PnvI2C, (obj), TYPE_PNV_I2C)
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#define PNV_I2C_REGS 0x20
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typedef struct PnvI2C {
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DeviceState parent;
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struct PnvChip *chip;
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qemu_irq psi_irq;
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uint64_t regs[PNV_I2C_REGS];
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uint32_t engine;
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uint32_t num_busses;
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I2CBus **busses;
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MemoryRegion xscom_regs;
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Fifo8 fifo;
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} PnvI2C;
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#endif /* PPC_PNV_I2C_H */
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