358 lines
11 KiB
C
358 lines
11 KiB
C
#ifndef QEMU_PCI_DEVICE_H
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#define QEMU_PCI_DEVICE_H
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#include "hw/pci/pci.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pcie_doe.h"
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#define TYPE_PCI_DEVICE "pci-device"
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typedef struct PCIDeviceClass PCIDeviceClass;
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DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
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PCI_DEVICE, TYPE_PCI_DEVICE)
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/*
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* Implemented by devices that can be plugged on CXL buses. In the spec, this is
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* actually a "CXL Component, but we name it device to match the PCI naming.
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*/
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#define INTERFACE_CXL_DEVICE "cxl-device"
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/* Implemented by devices that can be plugged on PCI Express buses */
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#define INTERFACE_PCIE_DEVICE "pci-express-device"
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/* Implemented by devices that can be plugged on Conventional PCI buses */
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#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
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struct PCIDeviceClass {
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DeviceClass parent_class;
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void (*realize)(PCIDevice *dev, Error **errp);
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PCIUnregisterFunc *exit;
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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uint16_t vendor_id;
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uint16_t device_id;
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uint8_t revision;
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uint16_t class_id;
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uint16_t subsystem_vendor_id; /* only for header type = 0 */
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uint16_t subsystem_id; /* only for header type = 0 */
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const char *romfile; /* rom bar */
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};
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enum PCIReqIDType {
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PCI_REQ_ID_INVALID = 0,
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PCI_REQ_ID_BDF,
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PCI_REQ_ID_SECONDARY_BUS,
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PCI_REQ_ID_MAX,
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};
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typedef enum PCIReqIDType PCIReqIDType;
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struct PCIReqIDCache {
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PCIDevice *dev;
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PCIReqIDType type;
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};
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typedef struct PCIReqIDCache PCIReqIDCache;
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struct PCIDevice {
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DeviceState qdev;
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bool partially_hotplugged;
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bool has_power;
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/* PCI config space */
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uint8_t *config;
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/*
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* Used to enable config checks on load. Note that writable bits are
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* never checked even if set in cmask.
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*/
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uint8_t *cmask;
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/* Used to implement R/W bytes */
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uint8_t *wmask;
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/* Used to implement RW1C(Write 1 to Clear) bytes */
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uint8_t *w1cmask;
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/* Used to allocate config space for capabilities. */
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uint8_t *used;
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/* the following fields are read only */
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int32_t devfn;
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/*
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* Cached device to fetch requester ID from, to avoid the PCI tree
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* walking every time we invoke PCI request (e.g., MSI). For
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* conventional PCI root complex, this field is meaningless.
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*/
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PCIReqIDCache requester_id_cache;
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char name[64];
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PCIIORegion io_regions[PCI_NUM_REGIONS];
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AddressSpace bus_master_as;
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MemoryRegion bus_master_container_region;
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MemoryRegion bus_master_enable_region;
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/* do not access the following fields */
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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/* Legacy PCI VGA regions */
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MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
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bool has_vga;
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/* Current IRQ levels. Used internally by the generic PCI code. */
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uint8_t irq_state;
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/* Capability bits */
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uint32_t cap_present;
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/* Offset of MSI-X capability in config space */
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uint8_t msix_cap;
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/* MSI-X entries */
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int msix_entries_nr;
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/* Space to store MSIX table & pending bit array */
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uint8_t *msix_table;
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uint8_t *msix_pba;
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/* May be used by INTx or MSI during interrupt notification */
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void *irq_opaque;
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MSITriggerFunc *msi_trigger;
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MSIPrepareMessageFunc *msi_prepare_message;
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MSIxPrepareMessageFunc *msix_prepare_message;
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/* MemoryRegion container for msix exclusive BAR setup */
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MemoryRegion msix_exclusive_bar;
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/* Memory Regions for MSIX table and pending bit entries. */
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MemoryRegion msix_table_mmio;
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MemoryRegion msix_pba_mmio;
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/* Reference-count for entries actually in use by driver. */
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unsigned *msix_entry_used;
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/* MSIX function mask set or MSIX disabled */
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bool msix_function_masked;
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/* Version id needed for VMState */
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int32_t version_id;
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/* Offset of MSI capability in config space */
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uint8_t msi_cap;
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/* PCI Express */
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PCIExpressDevice exp;
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/* SHPC */
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SHPCDevice *shpc;
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/* Location of option rom */
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char *romfile;
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uint32_t romsize;
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bool has_rom;
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MemoryRegion rom;
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uint32_t rom_bar;
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/* INTx routing notifier */
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PCIINTxRoutingNotifier intx_routing_notifier;
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/* MSI-X notifiers */
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MSIVectorUseNotifier msix_vector_use_notifier;
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MSIVectorReleaseNotifier msix_vector_release_notifier;
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MSIVectorPollNotifier msix_vector_poll_notifier;
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/* SPDM */
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uint16_t spdm_port;
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/* DOE */
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DOECap doe_spdm;
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/* ID of standby device in net_failover pair */
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char *failover_pair_id;
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uint32_t acpi_index;
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};
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static inline int pci_intx(PCIDevice *pci_dev)
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{
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return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
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}
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static inline int pci_is_cxl(const PCIDevice *d)
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{
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return d->cap_present & QEMU_PCIE_CAP_CXL;
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}
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static inline int pci_is_express(const PCIDevice *d)
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{
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return d->cap_present & QEMU_PCI_CAP_EXPRESS;
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}
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static inline int pci_is_express_downstream_port(const PCIDevice *d)
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{
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uint8_t type;
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if (!pci_is_express(d) || !d->exp.exp_cap) {
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return 0;
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}
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type = pcie_cap_get_type(d);
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return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
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}
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static inline int pci_is_vf(const PCIDevice *d)
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{
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return d->exp.sriov_vf.pf != NULL;
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}
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static inline uint32_t pci_config_size(const PCIDevice *d)
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{
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return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
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}
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static inline uint16_t pci_get_bdf(PCIDevice *dev)
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{
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return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
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}
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uint16_t pci_requester_id(PCIDevice *dev);
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/* DMA access functions */
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static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
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{
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return &dev->bus_master_as;
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}
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/**
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* pci_dma_rw: Read from or write to an address space from PCI device.
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*
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* Return a MemTxResult indicating whether the operation succeeded
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* or failed (eg unassigned memory, device rejected the transaction,
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* IOMMU fault).
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*
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* @dev: #PCIDevice doing the memory access
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* @addr: address within the #PCIDevice address space
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* @buf: buffer with the data transferred
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* @len: the number of bytes to read or write
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* @dir: indicates the transfer direction
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*/
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static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
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void *buf, dma_addr_t len,
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DMADirection dir, MemTxAttrs attrs)
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{
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return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
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dir, attrs);
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}
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/**
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* pci_dma_read: Read from an address space from PCI device.
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*
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* Return a MemTxResult indicating whether the operation succeeded
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* or failed (eg unassigned memory, device rejected the transaction,
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* IOMMU fault). Called within RCU critical section.
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*
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* @dev: #PCIDevice doing the memory access
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* @addr: address within the #PCIDevice address space
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* @buf: buffer with the data transferred
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* @len: length of the data transferred
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*/
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static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
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void *buf, dma_addr_t len)
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{
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return pci_dma_rw(dev, addr, buf, len,
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DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
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}
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/**
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* pci_dma_write: Write to address space from PCI device.
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*
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* Return a MemTxResult indicating whether the operation succeeded
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* or failed (eg unassigned memory, device rejected the transaction,
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* IOMMU fault).
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*
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* @dev: #PCIDevice doing the memory access
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* @addr: address within the #PCIDevice address space
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* @buf: buffer with the data transferred
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* @len: the number of bytes to write
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*/
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static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
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const void *buf, dma_addr_t len)
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{
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return pci_dma_rw(dev, addr, (void *) buf, len,
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DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
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}
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#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
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static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
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dma_addr_t addr, \
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uint##_bits##_t *val, \
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MemTxAttrs attrs) \
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{ \
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return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
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} \
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static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
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dma_addr_t addr, \
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uint##_bits##_t val, \
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MemTxAttrs attrs) \
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{ \
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return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
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}
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PCI_DMA_DEFINE_LDST(ub, b, 8);
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PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
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PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
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PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
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PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
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PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
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PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
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#undef PCI_DMA_DEFINE_LDST
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/**
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* pci_dma_map: Map device PCI address space range into host virtual address
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* @dev: #PCIDevice to be accessed
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* @addr: address within that device's address space
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* @plen: pointer to length of buffer; updated on return to indicate
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* if only a subset of the requested range has been mapped
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* @dir: indicates the transfer direction
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*
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* Return: A host pointer, or %NULL if the resources needed to
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* perform the mapping are exhausted (in that case *@plen
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* is set to zero).
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*/
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static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
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dma_addr_t *plen, DMADirection dir)
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{
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return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
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MEMTXATTRS_UNSPECIFIED);
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}
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static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
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DMADirection dir, dma_addr_t access_len)
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{
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dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
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}
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static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
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int alloc_hint)
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{
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qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
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}
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extern const VMStateDescription vmstate_pci_device;
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#define VMSTATE_PCI_DEVICE(_field, _state) { \
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.name = (stringify(_field)), \
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.size = sizeof(PCIDevice), \
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.vmsd = &vmstate_pci_device, \
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.flags = VMS_STRUCT, \
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.offset = vmstate_offset_value(_state, _field, PCIDevice), \
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}
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#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
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.name = (stringify(_field)), \
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.size = sizeof(PCIDevice), \
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.vmsd = &vmstate_pci_device, \
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.flags = VMS_STRUCT | VMS_POINTER, \
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.offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
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}
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#endif
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