85fc716732
As an implementation choice, widening VL has zeroed the previously inaccessible portion of the sve registers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180303143823.27055-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26 lines
606 B
C
26 lines
606 B
C
#ifndef AARCH64_TARGET_SYSCALL_H
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#define AARCH64_TARGET_SYSCALL_H
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struct target_pt_regs {
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uint64_t regs[31];
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uint64_t sp;
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uint64_t pc;
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uint64_t pstate;
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};
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#if defined(TARGET_WORDS_BIGENDIAN)
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#define UNAME_MACHINE "aarch64_be"
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#else
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#define UNAME_MACHINE "aarch64"
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#endif
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#define UNAME_MINIMUM_RELEASE "3.8.0"
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#define TARGET_CLONE_BACKWARDS
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#define TARGET_MINSIGSTKSZ 2048
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#define TARGET_MLOCKALL_MCL_CURRENT 1
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#define TARGET_MLOCKALL_MCL_FUTURE 2
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#define TARGET_PR_SVE_SET_VL 50
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#define TARGET_PR_SVE_GET_VL 51
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#endif /* AARCH64_TARGET_SYSCALL_H */
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