8e33944f8c
The bit that makes a dcbz instruction a dcbzl instruction was declared as reserved in ppc32 ISAs. However, hardware simply ignores the bit, making code valid if it simply invokes dcbzl instead of dcbz even on 750 and G4. Thus, mark the bit as unreserved so that we properly emulate a simple dcbz in case we're running on non-G5s. While at it, also refactor the code to check the 970 special case during runtime. This way we don't need to differenciate between a 970 dcbz and any other dcbz anymore. We also allow for future improvements to add e500mc dcbz handling. Reported-by: Amadeusz Sławiński <amade@asmblr.net> Signed-off-by: Alexander Graf <agraf@suse.de>
293 lines
9.2 KiB
C
293 lines
9.2 KiB
C
/*
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* PowerPC memory access emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "qemu/host-utils.h"
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#include "helper.h"
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#include "helper_regs.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "exec/softmmu_exec.h"
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#endif /* !defined(CONFIG_USER_ONLY) */
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//#define DEBUG_OP
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/*****************************************************************************/
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/* Memory load and stores */
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static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
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target_long arg)
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{
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#if defined(TARGET_PPC64)
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if (!msr_is_64bit(env, env->msr)) {
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return (uint32_t)(addr + arg);
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} else
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#endif
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{
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return addr + arg;
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}
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}
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void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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for (; reg < 32; reg++) {
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if (msr_le) {
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env->gpr[reg] = bswap32(cpu_ldl_data(env, addr));
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} else {
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env->gpr[reg] = cpu_ldl_data(env, addr);
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}
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addr = addr_add(env, addr, 4);
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}
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}
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void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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for (; reg < 32; reg++) {
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if (msr_le) {
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cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg]));
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} else {
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cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]);
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}
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addr = addr_add(env, addr, 4);
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}
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}
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void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
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{
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int sh;
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for (; nb > 3; nb -= 4) {
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env->gpr[reg] = cpu_ldl_data(env, addr);
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reg = (reg + 1) % 32;
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addr = addr_add(env, addr, 4);
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}
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if (unlikely(nb > 0)) {
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env->gpr[reg] = 0;
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for (sh = 24; nb > 0; nb--, sh -= 8) {
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env->gpr[reg] |= cpu_ldub_data(env, addr) << sh;
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addr = addr_add(env, addr, 1);
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}
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}
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}
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/* PPC32 specification says we must generate an exception if
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* rA is in the range of registers to be loaded.
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* In an other hand, IBM says this is valid, but rA won't be loaded.
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* For now, I'll follow the spec...
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*/
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void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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uint32_t ra, uint32_t rb)
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{
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if (likely(xer_bc != 0)) {
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if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
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(reg < rb && (reg + xer_bc) > rb))) {
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helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL |
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POWERPC_EXCP_INVAL_LSWX);
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} else {
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helper_lsw(env, addr, xer_bc, reg);
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}
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}
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}
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void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
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uint32_t reg)
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{
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int sh;
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for (; nb > 3; nb -= 4) {
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cpu_stl_data(env, addr, env->gpr[reg]);
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reg = (reg + 1) % 32;
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addr = addr_add(env, addr, 4);
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}
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if (unlikely(nb > 0)) {
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for (sh = 24; nb > 0; nb--, sh -= 8) {
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cpu_stb_data(env, addr, (env->gpr[reg] >> sh) & 0xFF);
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addr = addr_add(env, addr, 1);
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}
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}
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}
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static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size)
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{
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int i;
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addr &= ~(dcache_line_size - 1);
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for (i = 0; i < dcache_line_size; i += 4) {
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cpu_stl_data(env, addr + i, 0);
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}
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if (env->reserve_addr == addr) {
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env->reserve_addr = (target_ulong)-1ULL;
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}
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}
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void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl)
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{
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int dcbz_size = env->dcache_line_size;
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#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
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if (!is_dcbzl &&
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(env->excp_model == POWERPC_EXCP_970) &&
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((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
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dcbz_size = 32;
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}
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#endif
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/* XXX add e500mc support */
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do_dcbz(env, addr, dcbz_size);
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}
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void helper_icbi(CPUPPCState *env, target_ulong addr)
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{
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addr &= ~(env->dcache_line_size - 1);
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/* Invalidate one cache line :
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* PowerPC specification says this is to be treated like a load
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* (not a fetch) by the MMU. To be sure it will be so,
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* do the load "by hand".
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*/
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cpu_ldl_data(env, addr);
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}
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/* XXX: to be tested */
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target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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uint32_t ra, uint32_t rb)
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{
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int i, c, d;
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d = 24;
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for (i = 0; i < xer_bc; i++) {
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c = cpu_ldub_data(env, addr);
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addr = addr_add(env, addr, 1);
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/* ra (if not 0) and rb are never modified */
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if (likely(reg != rb && (ra == 0 || reg != ra))) {
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env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
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}
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if (unlikely(c == xer_cmp)) {
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break;
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}
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if (likely(d != 0)) {
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d -= 8;
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} else {
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d = 24;
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reg++;
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reg = reg & 0x1F;
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}
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}
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return i;
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}
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/*****************************************************************************/
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/* Altivec extension helpers */
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#if defined(HOST_WORDS_BIGENDIAN)
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#define HI_IDX 0
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#define LO_IDX 1
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#else
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#define HI_IDX 1
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#define LO_IDX 0
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#endif
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#define LVE(name, access, swap, element) \
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void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
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target_ulong addr) \
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{ \
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size_t n_elems = ARRAY_SIZE(r->element); \
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int adjust = HI_IDX*(n_elems - 1); \
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int sh = sizeof(r->element[0]) >> 1; \
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int index = (addr & 0xf) >> sh; \
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\
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if (msr_le) { \
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r->element[LO_IDX ? index : (adjust - index)] = \
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swap(access(env, addr)); \
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} else { \
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r->element[LO_IDX ? index : (adjust - index)] = \
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access(env, addr); \
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} \
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}
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#define I(x) (x)
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LVE(lvebx, cpu_ldub_data, I, u8)
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LVE(lvehx, cpu_lduw_data, bswap16, u16)
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LVE(lvewx, cpu_ldl_data, bswap32, u32)
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#undef I
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#undef LVE
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#define STVE(name, access, swap, element) \
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void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
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target_ulong addr) \
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{ \
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size_t n_elems = ARRAY_SIZE(r->element); \
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int adjust = HI_IDX * (n_elems - 1); \
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int sh = sizeof(r->element[0]) >> 1; \
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int index = (addr & 0xf) >> sh; \
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\
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if (msr_le) { \
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access(env, addr, swap(r->element[LO_IDX ? index : \
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(adjust - index)])); \
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} else { \
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access(env, addr, r->element[LO_IDX ? index : \
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(adjust - index)]); \
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} \
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}
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#define I(x) (x)
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STVE(stvebx, cpu_stb_data, I, u8)
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STVE(stvehx, cpu_stw_data, bswap16, u16)
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STVE(stvewx, cpu_stl_data, bswap32, u32)
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#undef I
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#undef LVE
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#undef HI_IDX
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#undef LO_IDX
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/*****************************************************************************/
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/* Softmmu support */
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#if !defined(CONFIG_USER_ONLY)
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#define MMUSUFFIX _mmu
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#define SHIFT 0
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#include "exec/softmmu_template.h"
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#define SHIFT 1
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#include "exec/softmmu_template.h"
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#define SHIFT 2
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#include "exec/softmmu_template.h"
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#define SHIFT 3
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#include "exec/softmmu_template.h"
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/* try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
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uintptr_t retaddr)
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{
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int ret;
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ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx);
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if (unlikely(ret != 0)) {
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if (likely(retaddr)) {
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/* now we have a real cpu fault */
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cpu_restore_state(env, retaddr);
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}
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helper_raise_exception_err(env, env->exception_index, env->error_code);
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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