qemu/target/arm/hvf
Peter Maydell f7ddd7b6a1 target/arm: Implement ID_AA64MMFR3_EL1
Newer versions of the Arm ARM (e.g.  rev K.a) now define fields for
ID_AA64MMFR3_EL1.  Implement this register, so that we can set the
fields if we need to.  There's no behaviour change here since we
don't currently set the register value to non-zero.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
2024-04-30 15:01:07 +01:00
..
hvf.c target/arm: Implement ID_AA64MMFR3_EL1 2024-04-30 15:01:07 +01:00
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
trace-events hvf: arm: Add support for GICv3 2023-02-03 12:59:22 +00:00