f478d9af21
This method is used to set up the interrupt backends for the current configuration. However, this means some confusing redirection between the "dual" mode init and the init hooks for xics only and xive only modes. Since we now have simple flags indicating whether XICS and/or XIVE are supported, it's easier to just open code each initialization directly in spapr_irq_init(). This will also make some future cleanups simpler. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
78 lines
2.8 KiB
C
78 lines
2.8 KiB
C
/*
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* QEMU PowerPC sPAPR IRQ backend definitions
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*
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* Copyright (c) 2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef HW_SPAPR_IRQ_H
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#define HW_SPAPR_IRQ_H
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#include "target/ppc/cpu-qom.h"
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/*
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* IRQ range offsets per device type
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*/
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#define SPAPR_IRQ_IPI 0x0
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#define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */
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#define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000)
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#define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001)
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#define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */
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#define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */
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/* Offset of the dynamic range covered by the bitmap allocator */
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#define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300)
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#define SPAPR_NR_XIRQS 0x1000
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#define SPAPR_NR_MSIS (SPAPR_XIRQ_BASE + SPAPR_NR_XIRQS - SPAPR_IRQ_MSI)
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typedef struct SpaprMachineState SpaprMachineState;
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void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis);
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int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
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Error **errp);
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void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
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typedef struct SpaprIrq {
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uint32_t nr_xirqs;
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uint32_t nr_msis;
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bool xics;
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bool xive;
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int (*claim)(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
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void (*free)(SpaprMachineState *spapr, int irq);
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void (*print_info)(SpaprMachineState *spapr, Monitor *mon);
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void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers,
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void *fdt, uint32_t phandle);
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void (*cpu_intc_create)(SpaprMachineState *spapr, PowerPCCPU *cpu,
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Error **errp);
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int (*post_load)(SpaprMachineState *spapr, int version_id);
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void (*reset)(SpaprMachineState *spapr, Error **errp);
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void (*set_irq)(void *opaque, int srcno, int val);
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void (*init_kvm)(SpaprMachineState *spapr, Error **errp);
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} SpaprIrq;
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extern SpaprIrq spapr_irq_xics;
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extern SpaprIrq spapr_irq_xics_legacy;
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extern SpaprIrq spapr_irq_xive;
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extern SpaprIrq spapr_irq_dual;
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void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
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int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
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void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
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qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
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int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
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void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
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int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
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/*
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* XICS legacy routines
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*/
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int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
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#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
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#endif
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