f404220e27
It's not what real HW does, implementing which would be overkill [**]
and would require complex cross stack changes (QEMU+firmware) to make
it work.
So considering that SMRAM is owned by MCH, for simplicity (ab)use
reserved Q35 register, which allows QEMU and firmware easily init
and make RAM at SMBASE available only from SMM context.
Patch uses commit (2f295167e0 q35/mch: implement extended TSEG sizes)
for inspiration and uses reserved register in config space at 0x9c
offset [*] to extend q35 pci-host with ability to use 128K at
0x30000 as SMRAM and hide it (like TSEG) from non-SMM context.
Usage:
1: write 0xff in the register
2: if the feature is supported, follow up read from the register
should return 0x01. At this point RAM at 0x30000 is still
available for SMI handler configuration from non-SMM context
3: writing 0x02 in the register, locks SMBASE area, making its contents
available only from SMM context. In non-SMM context, reads return
0xff and writes are ignored. Further writes into the register are
ignored until the system reset.
*) https://www.mail-archive.com/qemu-devel@nongnu.org/msg455991.html
**) https://www.mail-archive.com/qemu-devel@nongnu.org/msg646965.html
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <1575896942-331151-3-git-send-email-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
207 lines
8.1 KiB
C
207 lines
8.1 KiB
C
/*
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* q35.h
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*
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* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>
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*/
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#ifndef HW_Q35_H
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#define HW_Q35_H
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#include "hw/isa/isa.h"
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#include "hw/sysbus.h"
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#include "hw/i386/pc.h"
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#include "hw/isa/apm.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/ich9.h"
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#include "hw/pci-host/pam.h"
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#include "hw/i386/intel_iommu.h"
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#include "qemu/units.h"
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#define TYPE_Q35_HOST_DEVICE "q35-pcihost"
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#define Q35_HOST_DEVICE(obj) \
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OBJECT_CHECK(Q35PCIHost, (obj), TYPE_Q35_HOST_DEVICE)
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#define TYPE_MCH_PCI_DEVICE "mch"
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#define MCH_PCI_DEVICE(obj) \
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OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE)
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typedef struct MCHPCIState {
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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MemoryRegion *ram_memory;
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MemoryRegion *pci_address_space;
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MemoryRegion *system_memory;
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MemoryRegion *address_space_io;
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PAMMemoryRegion pam_regions[13];
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MemoryRegion smram_region, open_high_smram;
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MemoryRegion smram, low_smram, high_smram;
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MemoryRegion tseg_blackhole, tseg_window;
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MemoryRegion smbase_blackhole, smbase_window;
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bool has_smram_at_smbase;
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Range pci_hole;
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uint64_t below_4g_mem_size;
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uint64_t above_4g_mem_size;
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uint64_t pci_hole64_size;
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uint32_t short_root_bus;
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uint16_t ext_tseg_mbytes;
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} MCHPCIState;
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typedef struct Q35PCIHost {
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/*< private >*/
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PCIExpressHost parent_obj;
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/*< public >*/
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bool pci_hole64_fix;
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MCHPCIState mch;
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} Q35PCIHost;
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#define Q35_MASK(bit, ms_bit, ls_bit) \
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((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
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/*
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* gmch part
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*/
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#define MCH_HOST_PROP_RAM_MEM "ram-mem"
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#define MCH_HOST_PROP_PCI_MEM "pci-mem"
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#define MCH_HOST_PROP_SYSTEM_MEM "system-mem"
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#define MCH_HOST_PROP_IO_MEM "io-mem"
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/* PCI configuration */
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#define MCH_HOST_BRIDGE "MCH"
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#define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
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#define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
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/* D0:F0 configuration space */
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#define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0
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#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50
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#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE 2
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#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff
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#define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff
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#define MCH_HOST_BRIDGE_SMBASE_SIZE (128 * KiB)
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#define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000
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#define MCH_HOST_BRIDGE_F_SMBASE 0x9c
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#define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff
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#define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01
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#define MCH_HOST_BRIDGE_F_SMBASE_LCK 0x02
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#define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
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#define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
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#define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000
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#define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */
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#define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28)
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#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
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#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
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#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
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#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
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#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
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#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
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#define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
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#define MCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
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#define MCH_HOST_BRIDGE_PAM_NB 7
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#define MCH_HOST_BRIDGE_PAM_SIZE 7
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#define MCH_HOST_BRIDGE_PAM0 0x90
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#define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
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#define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */
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#define MCH_HOST_BRIDGE_PAM1 0x91
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#define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
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#define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
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#define MCH_HOST_BRIDGE_PAM2 0x92
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#define MCH_HOST_BRIDGE_PAM3 0x93
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#define MCH_HOST_BRIDGE_PAM4 0x94
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#define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
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#define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
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#define MCH_HOST_BRIDGE_PAM5 0x95
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#define MCH_HOST_BRIDGE_PAM6 0x96
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#define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
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#define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
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#define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
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#define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
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#define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
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#define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
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#define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
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#define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
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#define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
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#define MCH_HOST_BRIDGE_SMRAM 0x9d
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#define MCH_HOST_BRIDGE_SMRAM_SIZE 2
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#define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
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#define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
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#define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
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#define MCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
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#define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
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#define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
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#define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
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#define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
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#define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
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#define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
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#define MCH_HOST_BRIDGE_SMRAM_DEFAULT \
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MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG
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#define MCH_HOST_BRIDGE_SMRAM_WMASK \
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(MCH_HOST_BRIDGE_SMRAM_D_OPEN | \
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MCH_HOST_BRIDGE_SMRAM_D_CLS | \
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MCH_HOST_BRIDGE_SMRAM_D_LCK | \
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MCH_HOST_BRIDGE_SMRAM_G_SMRAME)
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#define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK \
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MCH_HOST_BRIDGE_SMRAM_D_CLS
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#define MCH_HOST_BRIDGE_ESMRAMC 0x9e
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#define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7))
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#define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 6))
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#define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 5))
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#define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 4))
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#define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 3))
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#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
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#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
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#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
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#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
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#define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1)
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#define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \
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(MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \
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MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \
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MCH_HOST_BRIDGE_ESMRAMC_SM_L2)
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#define MCH_HOST_BRIDGE_ESMRAMC_WMASK \
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(MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \
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MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \
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MCH_HOST_BRIDGE_ESMRAMC_T_EN)
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#define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0
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/* D1:F0 PCIE* port*/
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#define MCH_PCIE_DEV 1
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#define MCH_PCIE_FUNC 0
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uint64_t mch_mcfg_base(void);
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/*
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* Arbitrary but unique BNF number for IOAPIC device.
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*
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* TODO: make sure there would have no conflict with real PCI bus
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*/
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#define Q35_PSEUDO_BUS_PLATFORM (0xff)
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#define Q35_PSEUDO_DEVFN_IOAPIC (0x00)
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#endif /* HW_Q35_H */
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