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qemu/include/hw/riscv
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Bin Meng f3d47d5804
riscv: sifive_u: Set the minimum number of cpus to 2 
It is not useful if we only have one management CPU.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
[Palmer: Set default CPUs to 2]
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17 08:42:47 -07:00
..
boot.h
riscv: Add a helper routine for finding firmware
2019-09-17 08:42:43 -07:00
riscv_hart.h
riscv: hart: Add a "hartid-base" property to RISC-V hart array
2019-09-17 08:42:47 -07:00
riscv_htif.h
Clean up inclusion of sysemu/sysemu.h
2019-08-16 13:31:53 +02:00
sifive_clint.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00
sifive_cpu.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_e_prci.h
riscv: sifive_e: prci: Update the PRCI register block size
2019-09-17 08:42:46 -07:00
sifive_e.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_gpio.h
…
sifive_plic.h
riscv: plic: Remove unused interrupt functions
2019-09-17 08:42:42 -07:00
sifive_test.h
riscv: sifive_test: Add reset functionality
2019-09-17 08:42:44 -07:00
sifive_u.h
riscv: sifive_u: Set the minimum number of cpus to 2
2019-09-17 08:42:47 -07:00
sifive_uart.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00
spike.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00
virt.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00