8217606e6e
Add the parameter 'order' to qemu_register_reset and sort callbacks on registration. On system reset, callbacks with lower order will be invoked before those with higher order. Update all existing users to the standard order 0. Note: At least for x86, the existing users seem to assume that handlers are called in their registration order. Therefore, the patch preserves this property. If someone feels bored, (s)he could try to identify this dependency and express it properly on callback registration. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
665 lines
20 KiB
C
665 lines
20 KiB
C
/*
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* QEMU Crystal CS4231 audio chip emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "audiodev.h"
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#include "audio/audio.h"
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#include "isa.h"
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#include "qemu-timer.h"
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/*
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Missing features:
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ADC
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Loopback
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Timer
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ADPCM
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More...
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*/
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/* #define DEBUG */
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/* #define DEBUG_XLAW */
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static struct {
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int irq;
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int dma;
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int port;
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int aci_counter;
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} conf = {9, 3, 0x534, 1};
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#ifdef DEBUG
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#define dolog(...) AUD_log ("cs4231a", __VA_ARGS__)
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#else
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#define dolog(...)
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#endif
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#define lwarn(...) AUD_log ("cs4231a", "warning: " __VA_ARGS__)
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#define lerr(...) AUD_log ("cs4231a", "error: " __VA_ARGS__)
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#define CS_REGS 16
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#define CS_DREGS 32
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typedef struct CSState {
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QEMUSoundCard card;
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qemu_irq *pic;
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uint32_t regs[CS_REGS];
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uint8_t dregs[CS_DREGS];
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int irq;
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int dma;
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int port;
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int shift;
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int dma_running;
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int audio_free;
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int transferred;
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int aci_counter;
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SWVoiceOut *voice;
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int16_t *tab;
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} CSState;
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#define IO_READ_PROTO(name) \
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static uint32_t name (void *opaque, uint32_t addr)
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#define IO_WRITE_PROTO(name) \
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static void name (void *opaque, uint32_t addr, uint32_t val)
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#define GET_SADDR(addr) (addr & 3)
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#define MODE2 (1 << 6)
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#define MCE (1 << 6)
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#define PMCE (1 << 4)
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#define CMCE (1 << 5)
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#define TE (1 << 6)
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#define PEN (1 << 0)
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#define INT (1 << 0)
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#define IEN (1 << 1)
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#define PPIO (1 << 6)
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#define PI (1 << 4)
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#define CI (1 << 5)
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#define TI (1 << 6)
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enum {
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Index_Address,
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Index_Data,
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Status,
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PIO_Data
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};
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enum {
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Left_ADC_Input_Control,
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Right_ADC_Input_Control,
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Left_AUX1_Input_Control,
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Right_AUX1_Input_Control,
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Left_AUX2_Input_Control,
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Right_AUX2_Input_Control,
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Left_DAC_Output_Control,
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Right_DAC_Output_Control,
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FS_And_Playback_Data_Format,
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Interface_Configuration,
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Pin_Control,
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Error_Status_And_Initialization,
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MODE_And_ID,
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Loopback_Control,
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Playback_Upper_Base_Count,
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Playback_Lower_Base_Count,
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Alternate_Feature_Enable_I,
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Alternate_Feature_Enable_II,
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Left_Line_Input_Control,
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Right_Line_Input_Control,
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Timer_Low_Base,
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Timer_High_Base,
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RESERVED,
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Alternate_Feature_Enable_III,
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Alternate_Feature_Status,
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Version_Chip_ID,
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Mono_Input_And_Output_Control,
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RESERVED_2,
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Capture_Data_Format,
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RESERVED_3,
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Capture_Upper_Base_Count,
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Capture_Lower_Base_Count
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};
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static int freqs[2][8] = {
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{ 8000, 16000, 27420, 32000, -1, -1, 48000, 9000 },
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{ 5510, 11025, 18900, 22050, 37800, 44100, 33075, 6620 }
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};
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/* Tables courtesy http://hazelware.luggle.com/tutorials/mulawcompression.html */
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static int16_t MuLawDecompressTable[256] =
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{
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-32124,-31100,-30076,-29052,-28028,-27004,-25980,-24956,
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-23932,-22908,-21884,-20860,-19836,-18812,-17788,-16764,
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-15996,-15484,-14972,-14460,-13948,-13436,-12924,-12412,
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-11900,-11388,-10876,-10364, -9852, -9340, -8828, -8316,
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-7932, -7676, -7420, -7164, -6908, -6652, -6396, -6140,
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-5884, -5628, -5372, -5116, -4860, -4604, -4348, -4092,
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-3900, -3772, -3644, -3516, -3388, -3260, -3132, -3004,
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-2876, -2748, -2620, -2492, -2364, -2236, -2108, -1980,
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-1884, -1820, -1756, -1692, -1628, -1564, -1500, -1436,
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-1372, -1308, -1244, -1180, -1116, -1052, -988, -924,
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-876, -844, -812, -780, -748, -716, -684, -652,
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-620, -588, -556, -524, -492, -460, -428, -396,
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-372, -356, -340, -324, -308, -292, -276, -260,
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-244, -228, -212, -196, -180, -164, -148, -132,
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-120, -112, -104, -96, -88, -80, -72, -64,
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-56, -48, -40, -32, -24, -16, -8, 0,
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32124, 31100, 30076, 29052, 28028, 27004, 25980, 24956,
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23932, 22908, 21884, 20860, 19836, 18812, 17788, 16764,
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15996, 15484, 14972, 14460, 13948, 13436, 12924, 12412,
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11900, 11388, 10876, 10364, 9852, 9340, 8828, 8316,
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7932, 7676, 7420, 7164, 6908, 6652, 6396, 6140,
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5884, 5628, 5372, 5116, 4860, 4604, 4348, 4092,
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3900, 3772, 3644, 3516, 3388, 3260, 3132, 3004,
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2876, 2748, 2620, 2492, 2364, 2236, 2108, 1980,
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1884, 1820, 1756, 1692, 1628, 1564, 1500, 1436,
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1372, 1308, 1244, 1180, 1116, 1052, 988, 924,
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876, 844, 812, 780, 748, 716, 684, 652,
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620, 588, 556, 524, 492, 460, 428, 396,
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372, 356, 340, 324, 308, 292, 276, 260,
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244, 228, 212, 196, 180, 164, 148, 132,
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120, 112, 104, 96, 88, 80, 72, 64,
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56, 48, 40, 32, 24, 16, 8, 0
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};
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static int16_t ALawDecompressTable[256] =
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{
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-5504, -5248, -6016, -5760, -4480, -4224, -4992, -4736,
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-7552, -7296, -8064, -7808, -6528, -6272, -7040, -6784,
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-2752, -2624, -3008, -2880, -2240, -2112, -2496, -2368,
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-3776, -3648, -4032, -3904, -3264, -3136, -3520, -3392,
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-22016,-20992,-24064,-23040,-17920,-16896,-19968,-18944,
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-30208,-29184,-32256,-31232,-26112,-25088,-28160,-27136,
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-11008,-10496,-12032,-11520,-8960, -8448, -9984, -9472,
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-15104,-14592,-16128,-15616,-13056,-12544,-14080,-13568,
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-344, -328, -376, -360, -280, -264, -312, -296,
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-472, -456, -504, -488, -408, -392, -440, -424,
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-88, -72, -120, -104, -24, -8, -56, -40,
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-216, -200, -248, -232, -152, -136, -184, -168,
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-1376, -1312, -1504, -1440, -1120, -1056, -1248, -1184,
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-1888, -1824, -2016, -1952, -1632, -1568, -1760, -1696,
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-688, -656, -752, -720, -560, -528, -624, -592,
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-944, -912, -1008, -976, -816, -784, -880, -848,
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5504, 5248, 6016, 5760, 4480, 4224, 4992, 4736,
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7552, 7296, 8064, 7808, 6528, 6272, 7040, 6784,
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2752, 2624, 3008, 2880, 2240, 2112, 2496, 2368,
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3776, 3648, 4032, 3904, 3264, 3136, 3520, 3392,
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22016, 20992, 24064, 23040, 17920, 16896, 19968, 18944,
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30208, 29184, 32256, 31232, 26112, 25088, 28160, 27136,
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11008, 10496, 12032, 11520, 8960, 8448, 9984, 9472,
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15104, 14592, 16128, 15616, 13056, 12544, 14080, 13568,
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344, 328, 376, 360, 280, 264, 312, 296,
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472, 456, 504, 488, 408, 392, 440, 424,
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88, 72, 120, 104, 24, 8, 56, 40,
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216, 200, 248, 232, 152, 136, 184, 168,
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1376, 1312, 1504, 1440, 1120, 1056, 1248, 1184,
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1888, 1824, 2016, 1952, 1632, 1568, 1760, 1696,
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688, 656, 752, 720, 560, 528, 624, 592,
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944, 912, 1008, 976, 816, 784, 880, 848
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};
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static void cs_reset(void *opaque)
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{
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CSState *s = opaque;
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s->regs[Index_Address] = 0x40;
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s->regs[Index_Data] = 0x00;
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s->regs[Status] = 0x00;
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s->regs[PIO_Data] = 0x00;
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s->dregs[Left_ADC_Input_Control] = 0x00;
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s->dregs[Right_ADC_Input_Control] = 0x00;
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s->dregs[Left_AUX1_Input_Control] = 0x88;
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s->dregs[Right_AUX1_Input_Control] = 0x88;
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s->dregs[Left_AUX2_Input_Control] = 0x88;
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s->dregs[Right_AUX2_Input_Control] = 0x88;
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s->dregs[Left_DAC_Output_Control] = 0x80;
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s->dregs[Right_DAC_Output_Control] = 0x80;
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s->dregs[FS_And_Playback_Data_Format] = 0x00;
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s->dregs[Interface_Configuration] = 0x08;
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s->dregs[Pin_Control] = 0x00;
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s->dregs[Error_Status_And_Initialization] = 0x00;
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s->dregs[MODE_And_ID] = 0x8a;
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s->dregs[Loopback_Control] = 0x00;
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s->dregs[Playback_Upper_Base_Count] = 0x00;
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s->dregs[Playback_Lower_Base_Count] = 0x00;
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s->dregs[Alternate_Feature_Enable_I] = 0x00;
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s->dregs[Alternate_Feature_Enable_II] = 0x00;
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s->dregs[Left_Line_Input_Control] = 0x88;
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s->dregs[Right_Line_Input_Control] = 0x88;
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s->dregs[Timer_Low_Base] = 0x00;
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s->dregs[Timer_High_Base] = 0x00;
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s->dregs[RESERVED] = 0x00;
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s->dregs[Alternate_Feature_Enable_III] = 0x00;
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s->dregs[Alternate_Feature_Status] = 0x00;
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s->dregs[Version_Chip_ID] = 0xa0;
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s->dregs[Mono_Input_And_Output_Control] = 0xa0;
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s->dregs[RESERVED_2] = 0x00;
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s->dregs[Capture_Data_Format] = 0x00;
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s->dregs[RESERVED_3] = 0x00;
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s->dregs[Capture_Upper_Base_Count] = 0x00;
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s->dregs[Capture_Lower_Base_Count] = 0x00;
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}
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static void cs_audio_callback (void *opaque, int free)
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{
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CSState *s = opaque;
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s->audio_free = free;
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}
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static void cs_reset_voices (CSState *s, uint32_t val)
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{
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int xtal;
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struct audsettings as;
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#ifdef DEBUG_XLAW
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if (val == 0 || val == 32)
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val = (1 << 4) | (1 << 5);
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#endif
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xtal = val & 1;
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as.freq = freqs[xtal][(val >> 1) & 7];
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if (as.freq == -1) {
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lerr ("unsupported frequency (val=%#x)\n", val);
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goto error;
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}
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as.nchannels = (val & (1 << 4)) ? 2 : 1;
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as.endianness = 0;
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s->tab = NULL;
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switch ((val >> 5) & ((s->dregs[MODE_And_ID] & MODE2) ? 7 : 3)) {
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case 0:
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as.fmt = AUD_FMT_U8;
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s->shift = as.nchannels == 2;
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break;
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case 1:
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s->tab = MuLawDecompressTable;
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goto x_law;
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case 3:
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s->tab = ALawDecompressTable;
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x_law:
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as.fmt = AUD_FMT_S16;
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as.endianness = AUDIO_HOST_ENDIANNESS;
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s->shift = as.nchannels == 2;
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break;
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case 6:
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as.endianness = 1;
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case 2:
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as.fmt = AUD_FMT_S16;
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s->shift = as.nchannels;
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break;
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case 7:
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case 4:
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lerr ("attempt to use reserved format value (%#x)\n", val);
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goto error;
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case 5:
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lerr ("ADPCM 4 bit IMA compatible format is not supported\n");
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goto error;
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}
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s->voice = AUD_open_out (
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&s->card,
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s->voice,
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"cs4231a",
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s,
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cs_audio_callback,
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&as
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);
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if (s->dregs[Interface_Configuration] & PEN) {
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if (!s->dma_running) {
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DMA_hold_DREQ (s->dma);
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AUD_set_active_out (s->voice, 1);
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s->transferred = 0;
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}
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s->dma_running = 1;
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}
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else {
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if (s->dma_running) {
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DMA_release_DREQ (s->dma);
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AUD_set_active_out (s->voice, 0);
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}
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s->dma_running = 0;
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}
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return;
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error:
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if (s->dma_running) {
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DMA_release_DREQ (s->dma);
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AUD_set_active_out (s->voice, 0);
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}
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}
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IO_READ_PROTO (cs_read)
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{
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CSState *s = opaque;
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uint32_t saddr, iaddr, ret;
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saddr = GET_SADDR (addr);
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iaddr = ~0U;
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switch (saddr) {
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case Index_Address:
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ret = s->regs[saddr] & ~0x80;
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break;
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case Index_Data:
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if (!(s->dregs[MODE_And_ID] & MODE2))
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iaddr = s->regs[Index_Address] & 0x0f;
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else
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iaddr = s->regs[Index_Address] & 0x1f;
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ret = s->dregs[iaddr];
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if (iaddr == Error_Status_And_Initialization) {
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/* keep SEAL happy */
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if (s->aci_counter) {
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ret |= 1 << 5;
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s->aci_counter -= 1;
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}
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}
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break;
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default:
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ret = s->regs[saddr];
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break;
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}
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dolog ("read %d:%d -> %d\n", saddr, iaddr, ret);
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return ret;
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}
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IO_WRITE_PROTO (cs_write)
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{
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CSState *s = opaque;
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uint32_t saddr, iaddr;
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saddr = GET_SADDR (addr);
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switch (saddr) {
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case Index_Address:
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if (!(s->regs[Index_Address] & MCE) && (val & MCE)
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&& (s->dregs[Interface_Configuration] & (3 << 3)))
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s->aci_counter = conf.aci_counter;
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s->regs[Index_Address] = val & ~(1 << 7);
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break;
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case Index_Data:
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if (!(s->dregs[MODE_And_ID] & MODE2))
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iaddr = s->regs[Index_Address] & 0x0f;
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else
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iaddr = s->regs[Index_Address] & 0x1f;
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switch (iaddr) {
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case RESERVED:
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case RESERVED_2:
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case RESERVED_3:
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lwarn ("attempt to write %#x to reserved indirect register %d\n",
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val, iaddr);
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break;
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case FS_And_Playback_Data_Format:
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if (s->regs[Index_Address] & MCE) {
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cs_reset_voices (s, val);
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}
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else {
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if (s->dregs[Alternate_Feature_Status] & PMCE) {
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val = (val & ~0x0f) | (s->dregs[iaddr] & 0x0f);
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cs_reset_voices (s, val);
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}
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else {
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lwarn ("[P]MCE(%#x, %#x) is not set, val=%#x\n",
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s->regs[Index_Address],
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s->dregs[Alternate_Feature_Status],
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val);
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break;
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}
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}
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s->dregs[iaddr] = val;
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break;
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case Interface_Configuration:
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val &= ~(1 << 5); /* D5 is reserved */
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s->dregs[iaddr] = val;
|
|
if (val & PPIO) {
|
|
lwarn ("PIO is not supported (%#x)\n", val);
|
|
break;
|
|
}
|
|
if (val & PEN) {
|
|
if (!s->dma_running) {
|
|
cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]);
|
|
}
|
|
}
|
|
else {
|
|
if (s->dma_running) {
|
|
DMA_release_DREQ (s->dma);
|
|
AUD_set_active_out (s->voice, 0);
|
|
s->dma_running = 0;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case Error_Status_And_Initialization:
|
|
lwarn ("attempt to write to read only register %d\n", iaddr);
|
|
break;
|
|
|
|
case MODE_And_ID:
|
|
dolog ("val=%#x\n", val);
|
|
if (val & MODE2)
|
|
s->dregs[iaddr] |= MODE2;
|
|
else
|
|
s->dregs[iaddr] &= ~MODE2;
|
|
break;
|
|
|
|
case Alternate_Feature_Enable_I:
|
|
if (val & TE)
|
|
lerr ("timer is not yet supported\n");
|
|
s->dregs[iaddr] = val;
|
|
break;
|
|
|
|
case Alternate_Feature_Status:
|
|
if ((s->dregs[iaddr] & PI) && !(val & PI)) {
|
|
/* XXX: TI CI */
|
|
qemu_irq_lower (s->pic[s->irq]);
|
|
s->regs[Status] &= ~INT;
|
|
}
|
|
s->dregs[iaddr] = val;
|
|
break;
|
|
|
|
case Version_Chip_ID:
|
|
lwarn ("write to Version_Chip_ID register %#x\n", val);
|
|
s->dregs[iaddr] = val;
|
|
break;
|
|
|
|
default:
|
|
s->dregs[iaddr] = val;
|
|
break;
|
|
}
|
|
dolog ("written value %#x to indirect register %d\n", val, iaddr);
|
|
break;
|
|
|
|
case Status:
|
|
if (s->regs[Status] & INT) {
|
|
qemu_irq_lower (s->pic[s->irq]);
|
|
}
|
|
s->regs[Status] &= ~INT;
|
|
s->dregs[Alternate_Feature_Status] &= ~(PI | CI | TI);
|
|
break;
|
|
|
|
case PIO_Data:
|
|
lwarn ("attempt to write value %#x to PIO register\n", val);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int cs_write_audio (CSState *s, int nchan, int dma_pos,
|
|
int dma_len, int len)
|
|
{
|
|
int temp, net;
|
|
uint8_t tmpbuf[4096];
|
|
|
|
temp = len;
|
|
net = 0;
|
|
|
|
while (temp) {
|
|
int left = dma_len - dma_pos;
|
|
int copied;
|
|
size_t to_copy;
|
|
|
|
to_copy = audio_MIN (temp, left);
|
|
if (to_copy > sizeof (tmpbuf)) {
|
|
to_copy = sizeof (tmpbuf);
|
|
}
|
|
|
|
copied = DMA_read_memory (nchan, tmpbuf, dma_pos, to_copy);
|
|
if (s->tab) {
|
|
int i;
|
|
int16_t linbuf[4096];
|
|
|
|
for (i = 0; i < copied; ++i)
|
|
linbuf[i] = s->tab[tmpbuf[i]];
|
|
copied = AUD_write (s->voice, linbuf, copied << 1);
|
|
copied >>= 1;
|
|
}
|
|
else {
|
|
copied = AUD_write (s->voice, tmpbuf, copied);
|
|
}
|
|
|
|
temp -= copied;
|
|
dma_pos = (dma_pos + copied) % dma_len;
|
|
net += copied;
|
|
|
|
if (!copied) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
return net;
|
|
}
|
|
|
|
static int cs_dma_read (void *opaque, int nchan, int dma_pos, int dma_len)
|
|
{
|
|
CSState *s = opaque;
|
|
int copy, written;
|
|
int till = -1;
|
|
|
|
copy = s->voice ? (s->audio_free >> (s->tab != NULL)) : dma_len;
|
|
|
|
if (s->dregs[Pin_Control] & IEN) {
|
|
till = (s->dregs[Playback_Lower_Base_Count]
|
|
| (s->dregs[Playback_Upper_Base_Count] << 8)) << s->shift;
|
|
till -= s->transferred;
|
|
copy = audio_MIN (till, copy);
|
|
}
|
|
|
|
if ((copy <= 0) || (dma_len <= 0)) {
|
|
return dma_pos;
|
|
}
|
|
|
|
written = cs_write_audio (s, nchan, dma_pos, dma_len, copy);
|
|
|
|
dma_pos = (dma_pos + written) % dma_len;
|
|
s->audio_free -= (written << (s->tab != NULL));
|
|
|
|
if (written == till) {
|
|
s->regs[Status] |= INT;
|
|
s->dregs[Alternate_Feature_Status] |= PI;
|
|
s->transferred = 0;
|
|
qemu_irq_raise (s->pic[s->irq]);
|
|
}
|
|
else {
|
|
s->transferred += written;
|
|
}
|
|
|
|
return dma_pos;
|
|
}
|
|
|
|
static void cs_save(QEMUFile *f, void *opaque)
|
|
{
|
|
CSState *s = opaque;
|
|
unsigned int i;
|
|
uint32_t val;
|
|
|
|
for (i = 0; i < CS_REGS; i++)
|
|
qemu_put_be32s(f, &s->regs[i]);
|
|
|
|
qemu_put_buffer(f, s->dregs, CS_DREGS);
|
|
val = s->dma_running; qemu_put_be32s(f, &val);
|
|
val = s->audio_free; qemu_put_be32s(f, &val);
|
|
val = s->transferred; qemu_put_be32s(f, &val);
|
|
val = s->aci_counter; qemu_put_be32s(f, &val);
|
|
}
|
|
|
|
static int cs_load(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
CSState *s = opaque;
|
|
unsigned int i;
|
|
uint32_t val, dma_running;
|
|
|
|
if (version_id > 1)
|
|
return -EINVAL;
|
|
|
|
for (i = 0; i < CS_REGS; i++)
|
|
qemu_get_be32s(f, &s->regs[i]);
|
|
|
|
qemu_get_buffer(f, s->dregs, CS_DREGS);
|
|
|
|
qemu_get_be32s(f, &dma_running);
|
|
qemu_get_be32s(f, &val); s->audio_free = val;
|
|
qemu_get_be32s(f, &val); s->transferred = val;
|
|
qemu_get_be32s(f, &val); s->aci_counter = val;
|
|
if (dma_running && (s->dregs[Interface_Configuration] & PEN))
|
|
cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]);
|
|
return 0;
|
|
}
|
|
|
|
int cs4231a_init (qemu_irq *pic)
|
|
{
|
|
int i;
|
|
CSState *s;
|
|
|
|
s = qemu_mallocz (sizeof (*s));
|
|
|
|
s->pic = pic;
|
|
s->irq = conf.irq;
|
|
s->dma = conf.dma;
|
|
s->port = conf.port;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
register_ioport_write (s->port + i, 1, 1, cs_write, s);
|
|
register_ioport_read (s->port + i, 1, 1, cs_read, s);
|
|
}
|
|
|
|
DMA_register_channel (s->dma, cs_dma_read, s);
|
|
|
|
register_savevm ("cs4231a", 0, 1, cs_save, cs_load, s);
|
|
qemu_register_reset (cs_reset, 0, s);
|
|
cs_reset (s);
|
|
|
|
AUD_register_card ("cs4231a", &s->card);
|
|
return 0;
|
|
}
|