fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
81 lines
2.1 KiB
C
81 lines
2.1 KiB
C
/*
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* OpenRISC int helper routines
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Feng Gao <gf91597@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exception.h"
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#include "qemu/host-utils.h"
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target_ulong HELPER(ff1)(target_ulong x)
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{
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/*#ifdef TARGET_OPENRISC64
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return x ? ctz64(x) + 1 : 0;
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#else*/
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return x ? ctz32(x) + 1 : 0;
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/*#endif*/
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}
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target_ulong HELPER(fl1)(target_ulong x)
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{
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/* not used yet, open it when we need or64. */
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/*#ifdef TARGET_OPENRISC64
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return 64 - clz64(x);
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#else*/
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return 32 - clz32(x);
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/*#endif*/
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}
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uint32_t HELPER(mul32)(CPUOpenRISCState *env,
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uint32_t ra, uint32_t rb)
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{
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uint64_t result;
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uint32_t high, cy;
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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result = (uint64_t)ra * rb;
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/* regisiers in or32 is 32bit, so 32 is NOT a magic number.
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or64 is not handled in this function, and not implement yet,
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TARGET_LONG_BITS for or64 is 64, it will break this function,
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so, we didn't use TARGET_LONG_BITS here. */
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high = result >> 32;
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cy = result >> (32 - 1);
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if ((cy & 0x1) == 0x0) {
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if (high == 0x0) {
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return result;
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}
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}
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if ((cy & 0x1) == 0x1) {
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if (high == 0xffffffff) {
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return result;
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}
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}
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cpu->env.sr |= (SR_OV | SR_CY);
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if (cpu->env.sr & SR_OVE) {
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raise_exception(cpu, EXCP_RANGE);
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}
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return result;
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}
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