qemu/target/riscv/insn_trans
Philipp Tomsich f36a4a89aa target/riscv: Reassign instructions to the Zbs-extension
The following instructions are part of Zbs:
 - b{set,clr,ext,inv}
 - b{set,clr,ext,inv}i

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-07 08:33:13 +10:00
..
trans_privileged.c.inc riscv: Add semihosting support 2021-01-18 10:05:06 +00:00
trans_rva.c.inc target/riscv: Use {get,dest}_gpr for RVA 2021-09-01 11:59:12 +10:00
trans_rvb.c.inc target/riscv: Reassign instructions to the Zbs-extension 2021-10-07 08:33:13 +10:00
trans_rvd.c.inc target/riscv: Use {get,dest}_gpr for RVD 2021-09-01 11:59:12 +10:00
trans_rvf.c.inc target/riscv: Use {get,dest}_gpr for RVF 2021-09-01 11:59:12 +10:00
trans_rvh.c.inc target/riscv: Tidy trans_rvh.c.inc 2021-09-01 11:59:12 +10:00
trans_rvi.c.inc target/riscv: Reorg csr instructions 2021-09-01 11:59:12 +10:00
trans_rvm.c.inc target/riscv: Move gen_* helpers for RVM 2021-09-01 11:59:12 +10:00
trans_rvv.c.inc target/riscv: Use {get,dest}_gpr for RVV 2021-09-01 11:59:12 +10:00