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qemu/target/sparc/machine.c
Carl Hauser e412e9973a target/sparc: Add FQ and FSR.QNE 
Add support for, and migrate, a single-entry fp
instruction queue for sparc32.

Signed-off-by: Carl Hauser <chauser@pullman.com>
[rth: Split from a larger patch;
      adjust representation with union;
      add migration state]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Carl Hauser <chauser@pullman.com>
2024-09-11 19:54:35 -07:00

294 lines
8.8 KiB
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#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "qemu/timer.h"
#include "migration/cpu.h"
#ifdef TARGET_SPARC64
static const VMStateDescription vmstate_cpu_timer = {
.name = "cpu_timer",
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(frequency, CPUTimer),
VMSTATE_UINT32(disabled, CPUTimer),
VMSTATE_UINT64(disabled_mask, CPUTimer),
VMSTATE_UINT32(npt, CPUTimer),
VMSTATE_UINT64(npt_mask, CPUTimer),
VMSTATE_INT64(clock_offset, CPUTimer),
VMSTATE_TIMER_PTR(qtimer, CPUTimer),
VMSTATE_END_OF_LIST()
}
};
#define VMSTATE_CPU_TIMER(_f, _s) \
VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_timer, CPUTimer)
static const VMStateDescription vmstate_trap_state = {
.name = "trap_state",
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT64(tpc, trap_state),
VMSTATE_UINT64(tnpc, trap_state),
VMSTATE_UINT64(tstate, trap_state),
VMSTATE_UINT32(tt, trap_state),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_tlb_entry = {
.name = "tlb_entry",
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
VMSTATE_UINT64(tag, SparcTLBEntry),
VMSTATE_UINT64(tte, SparcTLBEntry),
VMSTATE_END_OF_LIST()
}
};
#endif
static int get_psr(QEMUFile *f, void *opaque, size_t size,
const VMStateField *field)
{
SPARCCPU *cpu = opaque;
CPUSPARCState *env = &cpu->env;
uint32_t val = qemu_get_be32(f);
/* needed to ensure that the wrapping registers are correctly updated */
env->cwp = 0;
cpu_put_psr_raw(env, val);
return 0;
}
static int put_psr(QEMUFile *f, void *opaque, size_t size,
const VMStateField *field, JSONWriter *vmdesc)
{
SPARCCPU *cpu = opaque;
CPUSPARCState *env = &cpu->env;
uint32_t val;
val = cpu_get_psr(env);
qemu_put_be32(f, val);
return 0;
}
static const VMStateInfo vmstate_psr = {
.name = "psr",
.get = get_psr,
.put = put_psr,
};
static int get_fsr(QEMUFile *f, void *opaque, size_t size,
const VMStateField *field)
{
SPARCCPU *cpu = opaque;
target_ulong val = qemu_get_betl(f);
cpu_put_fsr(&cpu->env, val);
return 0;
}
static int put_fsr(QEMUFile *f, void *opaque, size_t size,
const VMStateField *field, JSONWriter *vmdesc)
{
SPARCCPU *cpu = opaque;
target_ulong val = cpu_get_fsr(&cpu->env);
qemu_put_betl(f, val);
return 0;
}
static const VMStateInfo vmstate_fsr = {
.name = "fsr",
.get = get_fsr,
.put = put_fsr,
};
#ifdef TARGET_SPARC64
static int get_xcc(QEMUFile *f, void *opaque, size_t size,
const VMStateField *field)
{
SPARCCPU *cpu = opaque;
CPUSPARCState *env = &cpu->env;
uint32_t val = qemu_get_be32(f);
/* Do not clobber icc.[NV] */
env->cc_N = deposit64(env->cc_N, 32, 32, -(val & PSR_NEG));
env->cc_V = deposit64(env->cc_V, 32, 32, -(val & PSR_OVF));
env->xcc_Z = ~val & PSR_ZERO;
env->xcc_C = (val >> PSR_CARRY_SHIFT) & 1;
return 0;
}
static int put_xcc(QEMUFile *f, void *opaque, size_t size,
const VMStateField *field, JSONWriter *vmdesc)
{
SPARCCPU *cpu = opaque;
CPUSPARCState *env = &cpu->env;
uint32_t val = cpu_get_ccr(env);
/* Extract just xcc out of ccr and shift into legacy position. */
qemu_put_be32(f, (val & 0xf0) << (20 - 4));
return 0;
}
static const VMStateInfo vmstate_xcc = {
.name = "xcc",
.get = get_xcc,
.put = put_xcc,
};
#else
static bool fq_needed(void *opaque)
{
SPARCCPU *cpu = opaque;
return cpu->env.fsr_qne;
}
static const VMStateDescription vmstate_fq = {
.name = "cpu/fq",
.version_id = 1,
.minimum_version_id = 1,
.needed = fq_needed,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(env.fq.s.addr, SPARCCPU),
VMSTATE_UINT32(env.fq.s.insn, SPARCCPU),
VMSTATE_END_OF_LIST()
},
};
#endif
static int cpu_pre_save(void *opaque)
{
SPARCCPU *cpu = opaque;
CPUSPARCState *env = &cpu->env;
/* if env->cwp == env->nwindows - 1, this will set the ins of the last
* window as the outs of the first window
*/
cpu_set_cwp(env, env->cwp);
return 0;
}
/* 32-bit SPARC retains migration compatibility with older versions
* of QEMU; 64-bit SPARC has had a migration break since then, so the
* versions are different.
*/
#ifndef TARGET_SPARC64
#define SPARC_VMSTATE_VER 7
#else
#define SPARC_VMSTATE_VER 9
#endif
const VMStateDescription vmstate_sparc_cpu = {
.name = "cpu",
.version_id = SPARC_VMSTATE_VER,
.minimum_version_id = SPARC_VMSTATE_VER,
.pre_save = cpu_pre_save,
.fields = (const VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gregs, SPARCCPU, 8),
VMSTATE_UINT32(env.nwindows, SPARCCPU),
VMSTATE_VARRAY_MULTIPLY(env.regbase, SPARCCPU, env.nwindows, 16,
vmstate_info_uinttl, target_ulong),
VMSTATE_CPUDOUBLE_ARRAY(env.fpr, SPARCCPU, TARGET_DPREGS),
VMSTATE_UINTTL(env.pc, SPARCCPU),
VMSTATE_UINTTL(env.npc, SPARCCPU),
VMSTATE_UINTTL(env.y, SPARCCPU),
{
.name = "psr",
.version_id = 0,
.size = sizeof(uint32_t),
.info = &vmstate_psr,
.flags = VMS_SINGLE,
.offset = 0,
},
{
.name = "fsr",
.version_id = 0,
.size = sizeof(target_ulong),
.info = &vmstate_fsr,
.flags = VMS_SINGLE,
.offset = 0,
},
VMSTATE_UINTTL(env.tbr, SPARCCPU),
VMSTATE_INT32(env.interrupt_index, SPARCCPU),
VMSTATE_UINT32(env.pil_in, SPARCCPU),
#ifndef TARGET_SPARC64
/* MMU */
VMSTATE_UINT32(env.wim, SPARCCPU),
VMSTATE_UINT32_ARRAY(env.mmuregs, SPARCCPU, 32),
VMSTATE_UINT64_ARRAY(env.mxccdata, SPARCCPU, 4),
VMSTATE_UINT64_ARRAY(env.mxccregs, SPARCCPU, 8),
VMSTATE_UINT32(env.mmubpctrv, SPARCCPU),
VMSTATE_UINT32(env.mmubpctrc, SPARCCPU),
VMSTATE_UINT32(env.mmubpctrs, SPARCCPU),
VMSTATE_UINT64(env.mmubpaction, SPARCCPU),
VMSTATE_UINT64_ARRAY(env.mmubpregs, SPARCCPU, 4),
#else
VMSTATE_UINT64(env.lsu, SPARCCPU),
VMSTATE_UINT64_ARRAY(env.immu.mmuregs, SPARCCPU, 16),
VMSTATE_UINT64_ARRAY(env.dmmu.mmuregs, SPARCCPU, 16),
VMSTATE_STRUCT_ARRAY(env.itlb, SPARCCPU, 64, 0,
vmstate_tlb_entry, SparcTLBEntry),
VMSTATE_STRUCT_ARRAY(env.dtlb, SPARCCPU, 64, 0,
vmstate_tlb_entry, SparcTLBEntry),
VMSTATE_UINT32(env.mmu_version, SPARCCPU),
VMSTATE_STRUCT_ARRAY(env.ts, SPARCCPU, MAXTL_MAX, 0,
vmstate_trap_state, trap_state),
{
.name = "xcc",
.version_id = 0,
.size = sizeof(uint32_t),
.info = &vmstate_xcc,
.flags = VMS_SINGLE,
.offset = 0,
},
VMSTATE_UINT32(env.asi, SPARCCPU),
VMSTATE_UINT32(env.pstate, SPARCCPU),
VMSTATE_UINT32(env.tl, SPARCCPU),
VMSTATE_UINT32(env.cansave, SPARCCPU),
VMSTATE_UINT32(env.canrestore, SPARCCPU),
VMSTATE_UINT32(env.otherwin, SPARCCPU),
VMSTATE_UINT32(env.wstate, SPARCCPU),
VMSTATE_UINT32(env.cleanwin, SPARCCPU),
VMSTATE_UINT64_ARRAY(env.agregs, SPARCCPU, 8),
VMSTATE_UINT64_ARRAY(env.bgregs, SPARCCPU, 8),
VMSTATE_UINT64_ARRAY(env.igregs, SPARCCPU, 8),
VMSTATE_UINT64_ARRAY(env.mgregs, SPARCCPU, 8),
VMSTATE_UNUSED(4), /* was unused high half of uint64_t fprs */
VMSTATE_UINT32(env.fprs, SPARCCPU),
VMSTATE_UINT64(env.tick_cmpr, SPARCCPU),
VMSTATE_UINT64(env.stick_cmpr, SPARCCPU),
VMSTATE_CPU_TIMER(env.tick, SPARCCPU),
VMSTATE_CPU_TIMER(env.stick, SPARCCPU),
VMSTATE_UINT64(env.gsr, SPARCCPU),
VMSTATE_UINT32(env.gl, SPARCCPU),
VMSTATE_UINT64(env.hpstate, SPARCCPU),
VMSTATE_UINT64_ARRAY(env.htstate, SPARCCPU, MAXTL_MAX),
VMSTATE_UINT64(env.hintp, SPARCCPU),
VMSTATE_UINT64(env.htba, SPARCCPU),
VMSTATE_UINT64(env.hver, SPARCCPU),
VMSTATE_UINT64(env.hstick_cmpr, SPARCCPU),
VMSTATE_UINT64(env.ssr, SPARCCPU),
VMSTATE_CPU_TIMER(env.hstick, SPARCCPU),
/* On SPARC32 env.psrpil and env.cwp are migrated as part of the PSR */
VMSTATE_UINT32(env.psrpil, SPARCCPU),
VMSTATE_UINT32(env.cwp, SPARCCPU),
#endif
VMSTATE_END_OF_LIST()
},
#ifndef TARGET_SPARC64
.subsections = (const VMStateDescription * const []) {
&vmstate_fq,
NULL
},
#endif
};
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