Philipp Tomsich f2a32bec8f target/riscv: access cfg structure through DisasContext ... The Zb[abcs] support code still uses the RISCV_CPU macros to access the configuration information (i.e., check whether an extension is available/enabled). Now that we provide this information directly from DisasContext, we can access this directly via the cfg_ptr field. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220202005249.3566542-5-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-02-16 12:24:18 +10:00
..
trans_privileged.c.inc	target/riscv: Sign extend pc for different XLEN	2022-01-21 15:52:57 +10:00
trans_rva.c.inc	target/riscv: Calculate address according to XLEN	2022-01-21 15:52:57 +10:00
trans_rvb.c.inc	target/riscv: access cfg structure through DisasContext	2022-02-16 12:24:18 +10:00
trans_rvd.c.inc	target/riscv: Calculate address according to XLEN	2022-01-21 15:52:57 +10:00
trans_rvf.c.inc	target/riscv: Calculate address according to XLEN	2022-01-21 15:52:57 +10:00
trans_rvh.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvi.c.inc	target/riscv: access configuration through cfg_ptr in DisasContext	2022-02-16 12:24:18 +10:00
trans_rvm.c.inc	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
trans_rvv.c.inc	target/riscv: access configuration through cfg_ptr in DisasContext	2022-02-16 12:24:18 +10:00
trans_rvzfh.c.inc	target/riscv: access configuration through cfg_ptr in DisasContext	2022-02-16 12:24:18 +10:00