545d6bef70
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA transfers to and from DRAM. A pair of registers defines the buffer address and the length of the DMA transfer. The address should be aligned on 4 bytes and the maximum length should not exceed 4K. The receive or transmit DMA transfer can then be initiated with specific bits in the Command/Status register of the controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-5-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| aspeed_i2c.h | ||
| bitbang_i2c.h | ||
| i2c.h | ||
| imx_i2c.h | ||
| microbit_i2c.h | ||
| pm_smbus.h | ||
| ppc4xx_i2c.h | ||
| smbus_eeprom.h | ||
| smbus_master.h | ||
| smbus_slave.h | ||