f15af01740
Privileged spec section 4.1.9 mentions: "When a trap is taken into S-mode, stval is written with exception-specific information to assist software in handling the trap. (...) If stval is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then stval will contain the faulting virtual address." A similar text is found for mtval in section 3.1.16. Setting mtval/stval in this scenario is optional, but some softwares read these regs when handling ebreaks. Write 'badaddr' in all ebreak breakpoints to write the appropriate 'tval' during riscv_do_cpu_interrrupt(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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trans_privileged.c.inc | ||
trans_rva.c.inc | ||
trans_rvb.c.inc | ||
trans_rvbf16.c.inc | ||
trans_rvd.c.inc | ||
trans_rvf.c.inc | ||
trans_rvh.c.inc | ||
trans_rvi.c.inc | ||
trans_rvk.c.inc | ||
trans_rvm.c.inc | ||
trans_rvv.c.inc | ||
trans_rvvk.c.inc | ||
trans_rvzacas.c.inc | ||
trans_rvzawrs.c.inc | ||
trans_rvzce.c.inc | ||
trans_rvzfa.c.inc | ||
trans_rvzfh.c.inc | ||
trans_rvzicbo.c.inc | ||
trans_rvzicond.c.inc | ||
trans_svinval.c.inc | ||
trans_xthead.c.inc | ||
trans_xventanacondops.c.inc |