qemu/tcg/riscv
Richard Henderson f0f43534f7 tcg/riscv: Simplify constraints on qemu_ld/st
The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers.  Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11 09:53:41 +01:00
..
tcg-target-con-set.h tcg/riscv: Simplify constraints on qemu_ld/st 2023-05-11 09:53:41 +01:00
tcg-target-con-str.h tcg/riscv: Simplify constraints on qemu_ld/st 2023-05-11 09:53:41 +01:00
tcg-target.c.inc tcg/riscv: Simplify constraints on qemu_ld/st 2023-05-11 09:53:41 +01:00
tcg-target.h tcg/riscv: Require TCG_TARGET_REG_BITS == 64 2023-05-05 17:21:03 +01:00