12fde9bcdb
Add opcodes for backend support for 128-bit memory operations. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
159 lines
5.1 KiB
C
159 lines
5.1 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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* Copyright (c) 2008 Andrzej Zaborowski
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef ARM_TCG_TARGET_H
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#define ARM_TCG_TARGET_H
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extern int arm_arch;
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#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7)
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
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#define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX
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typedef enum {
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TCG_REG_R0 = 0,
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TCG_REG_R1,
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TCG_REG_R2,
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TCG_REG_R3,
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_PC,
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TCG_REG_Q0,
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TCG_REG_Q1,
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TCG_REG_Q2,
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TCG_REG_Q3,
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TCG_REG_Q4,
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TCG_REG_Q5,
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TCG_REG_Q6,
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TCG_REG_Q7,
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TCG_REG_Q8,
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TCG_REG_Q9,
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TCG_REG_Q10,
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TCG_REG_Q11,
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TCG_REG_Q12,
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TCG_REG_Q13,
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TCG_REG_Q14,
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TCG_REG_Q15,
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TCG_AREG0 = TCG_REG_R6,
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TCG_REG_CALL_STACK = TCG_REG_R13,
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} TCGReg;
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#define TCG_TARGET_NB_REGS 32
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#ifdef __ARM_ARCH_EXT_IDIV__
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#define use_idiv_instructions 1
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#else
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extern bool use_idiv_instructions;
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#endif
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#ifdef __ARM_NEON__
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#define use_neon_instructions 1
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#else
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extern bool use_neon_instructions;
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#endif
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/* used for function call generation */
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#define TCG_TARGET_STACK_ALIGN 8
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
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#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN
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#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
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#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF
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/* optional instructions */
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 0 /* and r0, r1, #0xff */
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_clz_i32 1
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#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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#define TCG_TARGET_HAS_muls2_i32 1
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#define TCG_TARGET_HAS_div_i32 use_idiv_instructions
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#define TCG_TARGET_HAS_rem_i32 0
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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#define TCG_TARGET_HAS_v64 use_neon_instructions
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#define TCG_TARGET_HAS_v128 use_neon_instructions
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#define TCG_TARGET_HAS_v256 0
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#define TCG_TARGET_HAS_andc_vec 1
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#define TCG_TARGET_HAS_orc_vec 1
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#define TCG_TARGET_HAS_nand_vec 0
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#define TCG_TARGET_HAS_nor_vec 0
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#define TCG_TARGET_HAS_eqv_vec 0
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#define TCG_TARGET_HAS_not_vec 1
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#define TCG_TARGET_HAS_neg_vec 1
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#define TCG_TARGET_HAS_abs_vec 1
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#define TCG_TARGET_HAS_roti_vec 0
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#define TCG_TARGET_HAS_rots_vec 0
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#define TCG_TARGET_HAS_rotv_vec 0
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 0
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#define TCG_TARGET_HAS_shv_vec 0
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 1
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#define TCG_TARGET_HAS_cmpsel_vec 0
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_NEED_LDST_LABELS
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#define TCG_TARGET_NEED_POOL_LABELS
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#endif
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