e3d0814368
Use device_class_set_legacy_reset() instead of opencoding an
assignment to DeviceClass::reset. This change was produced
with:
spatch --macro-file scripts/cocci-macro-file.h \
--sp-file scripts/coccinelle/device-reset.cocci \
--keep-comments --smpl-spacing --in-place --dir hw
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240830145812.1967042-8-peter.maydell@linaro.org
348 lines
10 KiB
C
348 lines
10 KiB
C
/*
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* STM32F2XX Timer
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/timer/stm32f2xx_timer.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#ifndef STM_TIMER_ERR_DEBUG
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#define STM_TIMER_ERR_DEBUG 0
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#endif
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#define DB_PRINT_L(lvl, fmt, args...) do { \
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if (STM_TIMER_ERR_DEBUG >= lvl) { \
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qemu_log("%s: " fmt, __func__, ## args); \
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} \
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} while (0)
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#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
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static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now);
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static void stm32f2xx_timer_interrupt(void *opaque)
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{
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STM32F2XXTimerState *s = opaque;
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DB_PRINT("Interrupt\n");
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if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) {
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s->tim_sr |= 1;
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qemu_irq_pulse(s->irq);
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stm32f2xx_timer_set_alarm(s, s->hit_time);
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}
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if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) &&
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!(s->tim_ccmr1 & TIM_CCMR1_OC2M0) &&
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s->tim_ccmr1 & TIM_CCMR1_OC2PE &&
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s->tim_ccer & TIM_CCER_CC2E) {
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/* PWM 2 - Mode 1 */
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DB_PRINT("PWM2 Duty Cycle: %d%%\n",
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s->tim_ccr2 / (100 * (s->tim_psc + 1)));
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}
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}
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static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)
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{
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return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1);
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}
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static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now)
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{
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uint64_t ticks;
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int64_t now_ticks;
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if (s->tim_arr == 0) {
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return;
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}
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DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1);
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now_ticks = stm32f2xx_ns_to_ticks(s, now);
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ticks = s->tim_arr - (now_ticks - s->tick_offset);
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DB_PRINT("Alarm set in %d ticks\n", (int) ticks);
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s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1),
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1000000000ULL, s->freq_hz);
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timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time);
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DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time);
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}
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static void stm32f2xx_timer_reset(DeviceState *dev)
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{
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STM32F2XXTimerState *s = STM32F2XXTIMER(dev);
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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s->tim_cr1 = 0;
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s->tim_cr2 = 0;
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s->tim_smcr = 0;
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s->tim_dier = 0;
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s->tim_sr = 0;
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s->tim_egr = 0;
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s->tim_ccmr1 = 0;
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s->tim_ccmr2 = 0;
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s->tim_ccer = 0;
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s->tim_psc = 0;
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s->tim_arr = 0;
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s->tim_ccr1 = 0;
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s->tim_ccr2 = 0;
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s->tim_ccr3 = 0;
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s->tim_ccr4 = 0;
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s->tim_dcr = 0;
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s->tim_dmar = 0;
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s->tim_or = 0;
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s->tick_offset = stm32f2xx_ns_to_ticks(s, now);
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}
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static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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STM32F2XXTimerState *s = opaque;
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DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset);
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switch (offset) {
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case TIM_CR1:
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return s->tim_cr1;
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case TIM_CR2:
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return s->tim_cr2;
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case TIM_SMCR:
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return s->tim_smcr;
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case TIM_DIER:
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return s->tim_dier;
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case TIM_SR:
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return s->tim_sr;
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case TIM_EGR:
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return s->tim_egr;
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case TIM_CCMR1:
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return s->tim_ccmr1;
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case TIM_CCMR2:
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return s->tim_ccmr2;
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case TIM_CCER:
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return s->tim_ccer;
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case TIM_CNT:
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return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) -
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s->tick_offset;
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case TIM_PSC:
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return s->tim_psc;
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case TIM_ARR:
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return s->tim_arr;
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case TIM_CCR1:
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return s->tim_ccr1;
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case TIM_CCR2:
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return s->tim_ccr2;
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case TIM_CCR3:
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return s->tim_ccr3;
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case TIM_CCR4:
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return s->tim_ccr4;
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case TIM_DCR:
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return s->tim_dcr;
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case TIM_DMAR:
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return s->tim_dmar;
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case TIM_OR:
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return s->tim_or;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
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}
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return 0;
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}
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static void stm32f2xx_timer_write(void *opaque, hwaddr offset,
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uint64_t val64, unsigned size)
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{
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STM32F2XXTimerState *s = opaque;
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uint32_t value = val64;
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint32_t timer_val = 0;
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DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset);
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switch (offset) {
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case TIM_CR1:
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s->tim_cr1 = value;
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return;
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case TIM_CR2:
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s->tim_cr2 = value;
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return;
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case TIM_SMCR:
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s->tim_smcr = value;
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return;
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case TIM_DIER:
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s->tim_dier = value;
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return;
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case TIM_SR:
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/* This is set by hardware and cleared by software */
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s->tim_sr &= value;
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return;
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case TIM_EGR:
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s->tim_egr = value;
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if (s->tim_egr & TIM_EGR_UG) {
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timer_val = 0;
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break;
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}
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return;
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case TIM_CCMR1:
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s->tim_ccmr1 = value;
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return;
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case TIM_CCMR2:
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s->tim_ccmr2 = value;
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return;
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case TIM_CCER:
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s->tim_ccer = value;
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return;
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case TIM_PSC:
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timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset;
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s->tim_psc = value & 0xFFFF;
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break;
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case TIM_CNT:
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timer_val = value;
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break;
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case TIM_ARR:
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s->tim_arr = value;
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stm32f2xx_timer_set_alarm(s, now);
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return;
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case TIM_CCR1:
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s->tim_ccr1 = value;
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return;
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case TIM_CCR2:
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s->tim_ccr2 = value;
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return;
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case TIM_CCR3:
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s->tim_ccr3 = value;
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return;
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case TIM_CCR4:
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s->tim_ccr4 = value;
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return;
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case TIM_DCR:
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s->tim_dcr = value;
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return;
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case TIM_DMAR:
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s->tim_dmar = value;
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return;
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case TIM_OR:
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s->tim_or = value;
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return;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
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return;
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}
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/* This means that a register write has affected the timer in a way that
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* requires a refresh of both tick_offset and the alarm.
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*/
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s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val;
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stm32f2xx_timer_set_alarm(s, now);
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}
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static const MemoryRegionOps stm32f2xx_timer_ops = {
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.read = stm32f2xx_timer_read,
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.write = stm32f2xx_timer_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_stm32f2xx_timer = {
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.name = TYPE_STM32F2XX_TIMER,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_INT64(tick_offset, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_dier, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_sr, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_egr, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_psc, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_arr, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState),
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VMSTATE_UINT32(tim_or, STM32F2XXTimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property stm32f2xx_timer_properties[] = {
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DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState,
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freq_hz, 1000000000),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void stm32f2xx_timer_init(Object *obj)
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{
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STM32F2XXTimerState *s = STM32F2XXTIMER(obj);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
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"stm32f2xx_timer", 0x400);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
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}
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static void stm32f2xx_timer_realize(DeviceState *dev, Error **errp)
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{
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STM32F2XXTimerState *s = STM32F2XXTIMER(dev);
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s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
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}
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static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_legacy_reset(dc, stm32f2xx_timer_reset);
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device_class_set_props(dc, stm32f2xx_timer_properties);
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dc->vmsd = &vmstate_stm32f2xx_timer;
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dc->realize = stm32f2xx_timer_realize;
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}
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static const TypeInfo stm32f2xx_timer_info = {
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.name = TYPE_STM32F2XX_TIMER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(STM32F2XXTimerState),
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.instance_init = stm32f2xx_timer_init,
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.class_init = stm32f2xx_timer_class_init,
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};
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static void stm32f2xx_timer_register_types(void)
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{
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type_register_static(&stm32f2xx_timer_info);
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}
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type_init(stm32f2xx_timer_register_types)
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