e92dd33224
accel/tcg/ files requires the following definitions: - TARGET_LONG_BITS - TARGET_PAGE_BITS - TARGET_PHYS_ADDR_SPACE_BITS - TCG_GUEST_DEFAULT_MO The first 3 are defined in "cpu-param.h". The last one in "cpu.h", with a bunch of definitions irrelevant for TCG. By moving the TCG_GUEST_DEFAULT_MO definition to "cpu-param.h", we can simplify various accel/tcg includes. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20231211212003.21686-4-philmd@linaro.org>
34 lines
791 B
C
34 lines
791 B
C
/*
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* RISC-V cpu parameters for qemu.
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*
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* Copyright (c) 2017-2018 SiFive, Inc.
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef RISCV_CPU_PARAM_H
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#define RISCV_CPU_PARAM_H
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#if defined(TARGET_RISCV64)
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# define TARGET_LONG_BITS 64
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# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
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# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
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#elif defined(TARGET_RISCV32)
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# define TARGET_LONG_BITS 32
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# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
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# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
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#endif
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#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
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/*
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* The current MMU Modes are:
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* - U mode 0b000
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* - S mode 0b001
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* - M mode 0b011
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* - U mode HLV/HLVX/HSV 0b100
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* - S mode HLV/HLVX/HSV 0b101
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* - M mode HLV/HLVX/HSV 0b111
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*/
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#define TCG_GUEST_DEFAULT_MO 0
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#endif
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