f03100d718
When system memory is larger than 1 GiB (high memory), PolarFire SoC maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is aliased to the same 1 GiB low memory with different cache attributes. At present QEMU maps the system memory contiguously from 0x8000_0000. This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is the alias to the high memory, and even physical memory is only 1 GiB, the HSS codes still tries to probe the high memory alias address. It seems there is no issue on the real hardware, so we will have to take that into the consideration in our emulation. Due to this, we we increase the default system memory size to 1537 MiB (the minimum required high memory size by HSS) so that user gets notified an error when less than 1537 MiB is specified. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201101170538.3732-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
147 lines
4.5 KiB
C
147 lines
4.5 KiB
C
/*
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* Microchip PolarFire SoC machine interface
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_MICROCHIP_PFSOC_H
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#define HW_MICROCHIP_PFSOC_H
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#include "hw/char/mchp_pfsoc_mmuart.h"
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#include "hw/dma/sifive_pdma.h"
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#include "hw/misc/mchp_pfsoc_dmc.h"
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#include "hw/misc/mchp_pfsoc_ioscb.h"
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#include "hw/misc/mchp_pfsoc_sysreg.h"
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#include "hw/net/cadence_gem.h"
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#include "hw/sd/cadence_sdhci.h"
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typedef struct MicrochipPFSoCState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CPUClusterState e_cluster;
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CPUClusterState u_cluster;
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RISCVHartArrayState e_cpus;
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RISCVHartArrayState u_cpus;
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DeviceState *plic;
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MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
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MchpPfSoCDdrCfgState ddr_cfg;
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MchpPfSoCIoscbState ioscb;
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MchpPfSoCMMUartState *serial0;
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MchpPfSoCMMUartState *serial1;
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MchpPfSoCMMUartState *serial2;
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MchpPfSoCMMUartState *serial3;
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MchpPfSoCMMUartState *serial4;
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MchpPfSoCSysregState sysreg;
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SiFivePDMAState dma;
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CadenceGEMState gem0;
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CadenceGEMState gem1;
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CadenceSDHCIState sdhci;
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} MicrochipPFSoCState;
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#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
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#define MICROCHIP_PFSOC(obj) \
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OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
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typedef struct MicrochipIcicleKitState {
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/*< private >*/
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MachineState parent_obj;
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/*< public >*/
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MicrochipPFSoCState soc;
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} MicrochipIcicleKitState;
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#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
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MACHINE_TYPE_NAME("microchip-icicle-kit")
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#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
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OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
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TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
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enum {
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MICROCHIP_PFSOC_RSVD0,
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MICROCHIP_PFSOC_DEBUG,
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MICROCHIP_PFSOC_E51_DTIM,
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MICROCHIP_PFSOC_BUSERR_UNIT0,
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MICROCHIP_PFSOC_BUSERR_UNIT1,
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MICROCHIP_PFSOC_BUSERR_UNIT2,
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MICROCHIP_PFSOC_BUSERR_UNIT3,
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MICROCHIP_PFSOC_BUSERR_UNIT4,
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MICROCHIP_PFSOC_CLINT,
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MICROCHIP_PFSOC_L2CC,
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MICROCHIP_PFSOC_DMA,
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MICROCHIP_PFSOC_L2LIM,
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MICROCHIP_PFSOC_PLIC,
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MICROCHIP_PFSOC_MMUART0,
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MICROCHIP_PFSOC_SYSREG,
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MICROCHIP_PFSOC_MPUCFG,
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MICROCHIP_PFSOC_DDR_SGMII_PHY,
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MICROCHIP_PFSOC_EMMC_SD,
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MICROCHIP_PFSOC_DDR_CFG,
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MICROCHIP_PFSOC_MMUART1,
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MICROCHIP_PFSOC_MMUART2,
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MICROCHIP_PFSOC_MMUART3,
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MICROCHIP_PFSOC_MMUART4,
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MICROCHIP_PFSOC_GEM0,
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MICROCHIP_PFSOC_GEM1,
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MICROCHIP_PFSOC_GPIO0,
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MICROCHIP_PFSOC_GPIO1,
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MICROCHIP_PFSOC_GPIO2,
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MICROCHIP_PFSOC_ENVM_CFG,
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MICROCHIP_PFSOC_ENVM_DATA,
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MICROCHIP_PFSOC_IOSCB,
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MICROCHIP_PFSOC_DRAM_LO,
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MICROCHIP_PFSOC_DRAM_LO_ALIAS,
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MICROCHIP_PFSOC_DRAM_HI,
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MICROCHIP_PFSOC_DRAM_HI_ALIAS
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};
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enum {
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MICROCHIP_PFSOC_DMA_IRQ0 = 5,
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MICROCHIP_PFSOC_DMA_IRQ1 = 6,
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MICROCHIP_PFSOC_DMA_IRQ2 = 7,
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MICROCHIP_PFSOC_DMA_IRQ3 = 8,
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MICROCHIP_PFSOC_DMA_IRQ4 = 9,
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MICROCHIP_PFSOC_DMA_IRQ5 = 10,
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MICROCHIP_PFSOC_DMA_IRQ6 = 11,
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MICROCHIP_PFSOC_DMA_IRQ7 = 12,
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MICROCHIP_PFSOC_GEM0_IRQ = 64,
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MICROCHIP_PFSOC_GEM1_IRQ = 70,
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MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
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MICROCHIP_PFSOC_MMUART0_IRQ = 90,
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MICROCHIP_PFSOC_MMUART1_IRQ = 91,
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MICROCHIP_PFSOC_MMUART2_IRQ = 92,
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MICROCHIP_PFSOC_MMUART3_IRQ = 93,
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MICROCHIP_PFSOC_MMUART4_IRQ = 94,
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};
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#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
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#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
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#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
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#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
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#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
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#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
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#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
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#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
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#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
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#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000
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#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000
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#endif /* HW_MICROCHIP_PFSOC_H */
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